Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

Senior ASIC engineer focused on physical design or static timing analysis (STA) for advanced AI/ML and high-performance compute silicon. The role is hands-on and supports customer ASIC programs from design through production, resolving implementation issues and ensuring tape-out quality.

Experience Level

Level: Senior. The posting does not specify an exact years-of-experience range but expects experienced engineers with multiple tape-outs and advanced-node exposure.

Responsibilities

Primary technical responsibilities and program support activities.

• Execute and support customer AI/ML ASIC programs across design, test, packaging, fabrication, bring-up, and production.
• Run physical design or STA validation flows to verify designs meet tape-out requirements for advanced nodes.
• Provide EDA tool, design-flow, and methodology guidance for high-performance silicon.
• Identify risks to quality, schedule, or dependencies and contribute to mitigation plans.
• Collaborate with cross-functional teams to resolve complex implementation challenges in compute and accelerator architectures.
• Support program communication between customers and internal partners.
• Stay current with AI silicon trends, IP, and implementation methodologies relevant to customer programs.

Requirements

Must-have technical skills and program constraints; nice-to-have items listed separately.

• Must-have: Hands-on physical design or STA experience with relevant EDA tools and flows.
• Multiple ASIC tape-outs (advanced nodes preferred) and strong PPA tradeoff understanding for high-performance designs.
• Knowledge of low-power design and power management in compute-intensive systems.
• Scripting experience (TCL, shell, or similar) and exposure to broader ASIC flows (logic simulation, test, packaging).
• Strong communication and collaboration skills; able to support customer-facing programs.
• Authorization requirement: must be currently authorized to work in the United States without sponsorship.

Nice-to-have:

• Experience with AI/ML accelerators, HPC, or large-scale compute SoCs.
• Exposure to SERDES or other high-speed interfaces.
• Experience in RTL design, microarchitecture, front-end flows, or DFT (scan, MBIST, repair).

Education Requirements

Not specified.

About the Company

Company: Everforth

Recruiting and staffing firm that posts technology and engineering job openings and partners with employers to fill roles across hardware and software, often supporting clients in semiconductor and AI industries.