Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

The Staff Physical Design Engineer owns complex block- and top-level physical implementation for advanced-node SoCs and provides technical leadership to a small team to deliver high-quality designs on schedule.

Works across floorplanning, power planning, placement, CTS, routing, verification and signoff, and collaborates with RTL, STA, DFT, CAD and packaging teams to meet PPA and release targets.

Experience Level

Senior — typically 8–12+ years of experience in physical design or equivalent technical mastery.

Responsibilities

Primary responsibilities include hands-on implementation, leading others, and improving physical-design flows:

• Own end-to-end physical implementation for complex blocks/subsystems (floorplan, power planning, placement, CTS, routing, ECO) on advanced nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).
• Drive timing closure, congestion resolution, IR/EM and signal-integrity fixes, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.
• Define and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.
• Analyze and debug tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.
• Develop and maintain physical-design methodologies, scripts and automation for PDN, PG, clock structures and signoff flows.
• Provide technical direction, review implementation choices, and mentor junior engineers to raise team capability.
• Represent physical-design status, risks and recommendations in design and signoff reviews; collaborate cross-functionally on architecture and constraints.
• Willingness to travel approximately 10% for project needs.

Requirements

Must-have technical skills and experience; followed by desirable additions.

• Proven hands-on expertise with industry-standard PNR and signoff tools (examples: Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus).
• Demonstrated success closing timing-, IR- and congestion-critical blocks/subsystems on advanced technology nodes.
• Deep understanding of floorplanning and partitioning strategies, power-grid/PDN methodology, IR/EM mitigation, and advanced clock-tree/clock-mesh design.
• Strong STA knowledge including modes/corners, exceptions and derates; familiarity with physical verification and reliability checks.
• Strong problem-solving and debugging skills, with emphasis on scalable automated solutions.
• Clear, concise communication skills and demonstrated experience mentoring and enabling other engineers.

Nice-to-have:

• Experience developing or enhancing physical-design flows or CAD enablement features.
• Prior leadership of a small technical team or technical ownership of large SoC subsystems.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.