Staff Physical Design Engineer
QualcommJob Title
Staff Physical Design Engineer
Role Summary
Senior physical-design engineer providing technical leadership for block-, die- and chip-level physical implementation on advanced FinFET nodes. Own the backend design methodology, drive automation, mentor engineers, and coordinate with foundry and EDA vendors.
Experience Level
Senior (Staff / Sr Staff). See Education Requirements for explicit degree-plus-experience guidance; candidates are expected to have multiple years of ASIC/physical-design experience and leadership responsibility.
Responsibilities
Deliver backend implementation and lead physical-design execution for SoC/IP projects.
- Define and own backend design methodology and implementation flows (block through full-chip).
- Lead floorplanning, place-and-route, ECOs, static timing analysis (STA), timing and power closure, and physical verification.
- Drive power-optimization strategies (DVFS, multi-Vt, power domains, UPF/CPF) and power analysis.
- Architect and implement large-scale SOC back-end automation and flow infrastructure.
- Perform complex simulations/analyses and tradeoffs for power, performance, and area.
- Prepare and review technical documentation; present readiness and risk assessments to senior management.
- Mentor and guide other engineers; collaborate with foundry, EDA vendors, and cross-functional stakeholders.
Requirements
Key required skills and experience (degrees and years summarized separately under Education Requirements).
- Deep expertise in floor-planning, place-and-route, ECO, STA, LEC, timing and power closure, and physical verification.
- Proven experience on advanced FinFET process nodes and full-chip implementation challenges.
- Strong scripting and automation skills (Shell, Python, Tcl) and experience building SOC back-end automation frameworks.
- Experience with power-optimization techniques and analysis tools.
- Ability to lead technical decisions, document designs, and communicate tradeoffs to engineering and executive audiences.
- Work independently with minimal supervision and provide technical guidance to team members.
Nice to have:
- Experience applying AI/LLM/agentic approaches to EDA challenges (autonomous agents, AI-driven optimization, LLM-assisted debugging).
- Prior direct collaboration with foundries and EDA vendors on process or tool flows.
Education Requirements
The posting references degree-plus-experience combinations. Examples extracted from the source include: Bachelor's degree in Science/Engineering (Computer Science, Electrical/Electronics, Computer Engineering, VLSI, Physics or related) with approximately 4–6+ years' ASIC/physical-design or hardware-engineering experience; Master's degree in a related field with roughly 3–5+ years' experience; PhD in a related field with roughly 2–4+ years' experience. Equivalent practical experience is accepted where noted.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
