Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

The Staff Physical Design Engineer owns complex block- and top-level physical implementation for advanced-node SoCs and leads a small team to deliver high-quality designs on schedule. Focus areas include floorplanning, power planning, placement, clock tree synthesis, routing, and signoff.

The role drives methodology improvements, tooling automation, and cross-functional coordination with RTL, STA, DFT, CAD, and packaging teams.

Experience Level

Senior level — typically 8–12+ years of experience in physical design or equivalent mastery.

Responsibilities

Key responsibilities include end-to-end implementation, methodology ownership, and technical leadership:

• Own floorplanning, power planning, placement, CTS, routing, and ECO for complex blocks or subsystems on advanced nodes (e.g., 22nm–4nm).
• Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA targets.
• Define hierarchical PNR strategies, IO ring/PG structures, and SoC integration guidelines.
• Analyze and debug tool issues, timing failures, and physical anomalies; propose scalable solutions.
• Develop and maintain physical design methodologies, scripts, and signoff automation.
• Evaluate EDA tool capabilities and collaborate with CAD/enablement to adopt best practices.
• Provide technical direction, review designs, and mentor junior engineers to raise team capability.
• Coordinate with RTL, STA, DFT, CAD, and packaging teams; present risks and recommendations in design reviews.

Requirements

Must-have technical skills and experience:

• Proven hands-on experience in physical design implementation for complex digital SoCs.
• Expertise with PNR and signoff tools (examples: Cadence Innovus, Synopsys ICC2, PrimeTime/Tempus, RedHawk, Voltus).
• Demonstrated experience closing timing-, IR-, and congestion-critical blocks on advanced nodes.
• Strong knowledge of floorplanning, partitioning, power grid/PDN methodology, clock tree/mesh design, STA constraints, and physical verification.
• Ability to develop scripts and flows to automate PDN, clocking, signoff, and exception handling.
• Strong problem-solving and debugging skills with a focus on scalable, automated solutions.
• Clear communication and mentoring experience; able to lead a small technical team.
• Willingness to travel up to 10%.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.