Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

Senior ASIC engineer responsible for hands-on physical design or STA support on advanced AI/ML and high-performance compute ASICs. Work directly with customer teams and internal engineering to drive designs from implementation through tape-out and production.

Onsite locations: San Jose, CA; Irvine, CA; Fort Collins, CO. Role emphasizes technical execution, EDA flow support, and risk identification/mitigation for high-performance silicon programs.

Experience Level

Senior-level (Staff). Candidates are expected to have substantial ASIC experience; multiple tape-outs or equivalent production program involvement is preferred.

Responsibilities

The role is primarily hands-on and focused on ensuring physical implementation and timing closure for advanced-node designs. Key responsibilities include:

• Support customer ASIC programs across design, test, packaging, fabrication, bring-up, and production.
• Execute physical design or STA validation flows to meet tape-out criteria for advanced nodes.
• Provide EDA tool and methodology guidance; implement and debug flows for high-performance designs.
• Identify schedule, quality, and dependency risks and drive mitigation actions.
• Collaborate with cross-functional teams to resolve implementation challenges in AI/compute architectures.
• Communicate program status and technical issues to customers and internal partners.

Requirements

Must-have technical skills and constraints for the role.

• Hands-on experience in physical design or STA on ASIC projects; experience with multiple tape-outs preferred.
• Strong understanding of PPA tradeoffs for high-performance designs and low-power design techniques.
• Familiarity with full ASIC flows (logic simulation, test, packaging) and related EDA tools and flows.
• Scripting proficiency (TCL, shell, or similar) for automation and flow development.
• Demonstrated ability to analyze EDA reports, debug implementation issues, and drive fixes to closure.
• Effective written and verbal communication for collaborating with customer and internal teams.
• Authorization to work in the United States without sponsorship is required for this position.

Nice-to-have:

• Experience with AI/ML accelerators, HPC, or large-scale compute SoCs.
• Exposure to SERDES or other high-speed interfaces.
• Background in RTL design, microarchitecture, DFT (scan, MBIST, repair) or front-end flows.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.