Staff Mixed-Signal Verification Engineer

Job Title

Staff Mixed-Signal Verification Engineer

Role Summary

Lead mixed-signal design and verification for complex ASICs (power management, signal management and mixed-signal functions). Develop verification environments, behavioral models, simulations and validation plans; work closely with analog design, layout, digital design, verification and physical teams. Role based in Porto (primary) with options for Barcelona or other Portugal locations.

Experience Level

Senior (Staff) level. Experience guidance: Staff - BSEE +12 years or MSEE +8 years; Senior - BSEE +7 years or MSEE +5 years.

Responsibilities

Lead verification and validation activities, supervise projects, and provide technical mentorship.

• Lead analog and mixed-signal verification and validation for ASIC projects.
• Define analog-digital interfaces and produce detailed documentation.
• Develop behavioral models of analog blocks to evaluate architecture and trade-offs.
• Define, develop, integrate and verify analog/mixed-signal IP.
• Run analog/digital mixed-signal simulations and perform debugging at transistor and behavioral levels.
• Support digital design on timing, I/O and DFT constraints; perform mixed-signal timing analysis.
• Support post-silicon validation and characterization activities.
• Supervise multiple projects to meet quality metrics, deliverables and schedules; mentor and train team members.
• Collaborate closely with analog design, layout, digital design, verification and physical engineering teams.

Requirements

Must-have technical skills and experience required for the role. Degree requirements are listed under Education Requirements.

• Extensive experience in transistor-level and analog/mixed-signal circuit design and verification.
• Strong understanding of device mismatch, noise, linearity, stability and other analog effects.
• Experience with SPICE-like simulators (Spectre, HSPICE) and Cadence ADE-L/ADE-XL.
• Experience with complex simulations: Monte Carlo, noise and stability analyses.
• Experience with Verilog-AMS mixed-mode simulation and coding in Verilog / SystemVerilog / Verilog-A for behavioral modeling.
• Practical knowledge of layout best practices and DRC/LVS tools such as Calibre or ICV.
• Familiarity with DFT techniques (SCAN, LBIST, ABIST, IDDQ) and STA / I/O timing for synthesis and P&R.
• Proven leadership, project supervision and cross-functional collaboration skills.

Nice-to-have:

• Automotive ASIL experience and power-management industry knowledge.
• Experience with serial interfaces and protocols: I2C, I3C, SPI, USB, PMBUS.
• Familiarity with version control and design-data tools: GitLab, Cliosoft SOS.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or Master of Science in Electrical Engineering (MSEE) with the following experience mappings: Staff position - BSEE +12 years or MSEE +8 years; Senior position - BSEE +7 years or MSEE +5 years. No alternative equivalent-degree language or other academic certifications were specified.

About the Company

Company: Monolithic Power Systems

Headquarters: San Jose, California, USA

Monolithic Power Systems, Inc. (MPS) is a leading provider of energy-efficient power solutions for various applications, including industrial, telecom, automotive, and consumer sectors. Known for their cutting-edge integrated power semiconductors, MPS emphasizes innovation, sustainability, and creativity, making them one of the fastest-growing companies in the semiconductor industry.