Staff Logic Design Engineer

Job Title

Staff Logic Design Engineer

Role Summary

The Devices Development Group Malaysia (DDG-MYS) Client SoC Team seeks a Staff Logic Design Engineer to design, integrate, and deliver RTL/IP for Intel Client SoC platforms. This role focuses on high-performance IP development, IP-to-SoC integration, and ensuring front-end design quality for downstream integration.

Experience Level

Level - Senior. The posting specifies at least 3 years of experience in IP or SoC RTL/Logic design; the role expects senior-level ownership of IP design and SoC integration activities.

Responsibilities

Primary responsibilities include RTL/IP design, integration, and front-end quality assurance for Client SoCs.

• Own internal IP RTL design and development or integrate high-performance, high-bandwidth IP into Client SoC platforms.
• Define, implement, and deliver new IP features, change requests, and feature enhancements.
• Drive IP-to-SoC handoff quality: ensure design completeness, compliance, and readiness for downstream teams.
• Perform logic and RTL integration into SoC, including power intent definition and signal handling across power planes and clock domains.
• Provide front-end collateral required for system and software integration.
• Collaborate with verification teams to validate functionality, features, and integration readiness.
• Execute RTL front-end quality checks: static analysis, synthesizability, timing and power convergence, netlist quality, and formal equivalence verification.

Requirements

Key technical and professional requirements. Degree details are listed separately under Education Requirements.

• Must-have:
  • Strong RTL design experience using Verilog and SystemVerilog.
  • Experience with SoC/ASIC front-end design methodology and industry-standard RTL flows and tools.
  • Knowledge of IP/subsystem architecture, I/O architecture, and common high-speed bus protocols.
  • Experience with SoC fabric and interconnect design and RTL integration across power and clock domains.
  • Pre-silicon or post-silicon lab debug and power-on experience.
  • Ability to use automation and scripting to orchestrate efficient development workflows.
  • Strong communication, collaboration, problem-solving, and teamwork skills.
• Nice-to-have:
  • Familiarity with AI-assisted engineering workflows to improve RTL/Logic development productivity (design exploration, code generation, review, debug, documentation, and front-end quality checks).

Education Requirements

Bachelor's or Master's degree in Electrical and Electronic Engineering, Computer Engineering, Computer Science, or a related discipline (as stated in the posting). The posting specifies at least 3 years of relevant IP or SoC RTL/Logic design experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.