Staff Layout Engineer – DDR/HBM PHY IP

Role Summary

The Staff Layout Engineer will lead the design and development of next-generation DDR and HBM PHY IP layouts, driving technical innovation and mentoring junior engineers within a world-class Silicon IP team.

Experience Level

Senior level with a minimum of 5 years of relevant experience in physical layout design, particularly in advanced nodes of 7nm and below.

Responsibilities

The key responsibilities include:

• Leading the design and development of DDR and HBM PHY IP layout.
• Providing mentorship to junior engineers.
• Managing layout planning, execution, and quality reviews.
• Collaborating with circuit design, verification, and engineering teams.
• Reviewing and optimizing layout for advanced process technologies.
• Supporting phases like floorplanning and bond-pad layout.

Requirements

The following qualifications are required:

• BTech/MTech degree in Electronics, Electrical Engineering, or a related field.
• Minimum 5 years of experience in physical layout design.
• Expertise in advanced process technologies and layout matching.
• Proficiency in EDA tools for layout and verification.

Education Requirements

A Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related field is required.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.