Staff Layout Engineer

Role Summary

The Staff Layout Engineer will lead the development of advanced DDR and HBM layout IPs while mentoring junior engineers. This role requires strong technical expertise in layout design and a commitment to delivering high-quality solutions.

Experience Level

Mid-level; 5+ years of relevant experience in layout design is required.

Responsibilities

The main responsibilities include:

• Leading the development of DDR and HBM layout IPs, setting technical direction and standards.
• Providing hands-on expertise in layout creation and troubleshooting.
• Mentoring junior engineers and fostering technical excellence.
• Estimating project efforts and planning schedules.
• Collaborating with teams for layout requirements and quality assurance.
• Conducting layout reviews to ensure compliance with customer requirements.

Requirements

Key requirements include:

• Degree in Electronics, Electrical Engineering, or a related field (BTech/MTech).
• 5+ years' experience in layout design, especially in DDR and HBM PHY IP development.
• Deep understanding of CMOS, FinFET, and GAA technologies at 7nm and below.
• Expertise in layout matching, ESD, latch-up, and related technical areas.
• Strong leadership and communication skills.

Education Requirements

BTech/MTech in Electronics, Electrical Engineering, or related field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.