Staff IP Design Engineer

Job Title

Staff IP Design Engineer

Role Summary

Join the Penang IP team to lead research, design and delivery of Lattice Foundation IP, FPGA primitives, and related EDA design flow components. The role focuses on developing robust, safety-ready IP, coordinating cross-functional release activities, and improving verification and validation processes.

Work includes requirement analysis, feature scoping, RTL and testbench development, timing closure, debugging, and producing IP release artifacts.

Experience Level

Senior — typically requires 8+ years of experience in FPGA IP and/or EDA tools development.

Responsibilities

The engineer will take technical ownership of IP features and releases and provide cross-team leadership to ensure product robustness and safety readiness.

• Lead research, design and development of FPGA primitives and Foundation IP.
• Develop and maintain FPGA EDA design flow and device modeling for soft IP.
• Plan and execute IP release cycles: requirements analysis, feature scoping, development, testing, and validation.
• Implement RTL designs, create testbenches, perform logic verification and timing closure across multi-clock domains.
• Perform systematic root-cause debugging of functional and timing issues and drive resolutions.
• Ensure IP-level functional safety readiness and generate audit-ready safety evidence when required.
• Collaborate with cross-functional teams and mentor junior engineers; influence engineering decisions and best practices.

Requirements

Key must-have technical skills and experience; preferred items listed separately.

• Must-have: 8+ years of hands-on experience in FPGA IP development and/or EDA tool development.
• Practical experience with FPGA architecture and software tools for device modeling and soft IP development.
• Hands-on RTL design, testbench development, logic verification, timing closure across multi-clock domains, and systematic root-cause debugging.
• Strong communication skills and ability to work with cross-functional teams.
• Demonstrated technical leadership and accountability for multi-project outcomes.
• Nice-to-have: Expertise in specific FPGA primitives (e.g., block RAM, DSP, PLL, I/O, configuration/security, power features).
• Experience developing safety-related SoC or FPGA soft IP and producing functional safety evidence compliant with standards such as IEC 61508 or ISO 26262.

Education Requirements

Bachelor's, Master's or higher in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field is specified. The posting pairs these degree qualifications with a requirement of 8+ years of relevant experience.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.