Staff IC Packaging Engineer - Mechanical Simulation

Job Title

Staff IC Packaging Engineer - Mechanical Simulation

Role Summary

Member of the IC package engineering process team providing mechanical finite element analysis (FEA) support for high-volume manufacturing (HVM) and advanced IC packaging technologies. Works with design, new product introduction (NPI) and chip-package interaction (CPI) teams to predict and mitigate mechanical failures and guide package design.

Experience Level

Senior-level. Preferred: 6+ years of FEA modeling for IC packages and 4+ years in the semiconductor/IC packaging industry. Minimum experience varies by degree (see Education Requirements).

Responsibilities

Provide mechanical simulation and FEA-driven guidance across package design and manufacturing.

• Develop and maintain mechanical FEA models and APDL/workbench workflows for IC packages.
• Perform warpage and stress analysis, solder joint reliability (SJR) prediction, and package assembly process simulations.
• Run chip-package interaction (CPI) and package-board interaction analyses to predict failure modes.
• Use advanced FEA techniques (sub-modeling, contact, non-linear analysis) and establish best-known-methods (BKMs) for predictive modeling and test correlation.
• Lead material characterization/testing activities and develop test methods to improve model accuracy and correlation.
• Collaborate with cross-functional teams (design, NPI, CPI) and communicate results to engineering and manufacturing stakeholders.
• Maintain and improve simulation automation and macros; mentor colleagues on simulation practices.

Requirements

Core technical skills and professional capabilities required for the role.

• Proven FEA modeling experience for IC electronic packages and interconnects, including warpage and reliability analysis.
• Hands-on experience with ANSYS APDL and Workbench for model development and automation (multi-year usage expected).
• Practical knowledge of solder joint reliability prediction, CPI/package-board interaction, and assembly process simulation.
• Ability to apply advanced FEA methods: sub-modeling, contact formulations, non-linear material/geometry behavior.
• Experience in material characterization, test correlation, and developing BKMs for predictive accuracy.
• Strong analytical, project execution, communication and presentation skills; able to work across time zones and support APAC/U.S. collaboration.
• Willingness to travel occasionally for domestic and international collaboration or testing.
• Nice-to-have: experience with DOE, research/publications in FEA or reliability, and use of AI tools to accelerate APDL coding and simulation workflows.

Education Requirements

Minimum: Bachelor's degree in Chemical, Electrical, Mechanical Engineering or related field plus 4+ years of relevant system/package design or technology engineering experience; OR Master's degree in those fields plus 3+ years; OR PhD in those fields plus 2+ years. Preferred fields include Mechanical Engineering, Materials Science, Electrical/Microelectronics or related engineering disciplines. Equivalent practical experience is acceptable where stated.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.