Staff Hardware Design Engineer (F/M)
ArterisIPJob Title
Staff Hardware Design Engineer (F/M)
Role Summary
Senior hardware design engineer responsible for designing and delivering configurable network-on-chip (NoC) IP components for Arteris. Acts as a technical lead on complex RTL and architecture tasks, works across hardware, software, and verification teams, and mentors junior engineers.
Experience Level
Senior — typically 8–12 years of experience in SoC/IP/NoC design.
Responsibilities
Core responsibilities include architecture, RTL design, verification, and cross-team collaboration.
- Design and develop complex hardware blocks for configurable IPs, including RTL coding and performance optimization.
- Define architecture specifications for NoC components and propose improvements.
- Create verification environments and functional coverage strategies.
- Resolve complex technical problems and provide technical support to team members.
- Collaborate with hardware, software, and verification teams for component integration.
- Improve team design and verification methodologies and document designs.
- Engage in technical customer discussions and mentor junior engineers.
Requirements
Must-have technical skills and experience.
- 8–12 years of experience in SoC/IP/NoC design.
- Strong expertise in coherent and non‑coherent protocols such as AMBA/AXI/ACE, PCIe, CXL, CHI, or similar.
- Deep understanding of CPU architectures (ARM, RISC‑V), cache systems, and memory coherence.
- Experience across the SoC/IP design flow: specification, architecture, RTL coding, verification, synthesis, DFT, timing and power constraints.
- Advanced Verilog/SystemVerilog skills and experience with common simulation/synthesis toolchains (Cadence, Synopsys, Mentor).
- Proficiency in SystemC, C++, Python, and scripting for modeling and automation.
- Strong problem‑solving, communication, and independent working skills; fluent in English.
Education Requirements
Master’s degree (or equivalent practical experience) in Electrical Engineering, Computer Science, or a related technical field.
About the Company
Company: ArterisIP
Headquarters: Montigny-le-Bretonneux, France
Provider of configurable on-chip interconnect IP and network-on-chip (NoC) solutions for system-on-chip (SoC) integration, offering interconnect fabrics, IP blocks, verification tools and engineering support to semiconductor and system companies.
