Staff FPGA Verification Engineer

Job Title

Staff FPGA Verification Engineer

Role Summary

Senior engineering role on the FPGA team responsible for verification of FPGA designs and associated hardware-software interfaces. The position supports development, validation, and release of flight or mission-critical FPGA firmware and verification infrastructure.

Works closely with FPGA designers, firmware and systems engineers to define verification plans, execute test campaigns, and support lab bring-up and debugging.

Experience Level

Senior-level. The posting uses the title "Staff" and targets experienced verification engineers; no specific years of experience are stated.

Responsibilities

Primary responsibilities include planning and executing verification for FPGA designs and supporting hardware integration.

• Develop verification strategies and detailed verification plans for FPGA subsystems.
• Implement and maintain testbenches, assertions, and directed/random test suites (e.g., SystemVerilog/UVM).
• Run simulations, formal checks, and linters; analyze results and track coverage metrics.
• Integrate verification with CI systems and scripting frameworks for automated regression testing.
• Support lab bring-up and debug of FPGA hardware, including root-cause analysis and on-hardware validation.
• Mentor junior engineers and collaborate across cross-functional teams to meet release schedules.

Requirements

Key qualifications and constraints for candidates.

• Must-have: Proven experience in FPGA verification (writing testbenches, simulation, coverage analysis) and familiarity with SystemVerilog and verification methodologies.
• Must-have: Hands-on experience with simulation tools and scripting for automation (for example: ModelSim/Questa/other simulators, Python or similar).
• Must-have: Ability to perform hardware bring-up and debugging on FPGA platforms; experience with lab equipment and on-target validation.
• Must-have: Eligible to work as a U.S. Person or able to obtain required export authorization (per hiring policy for this role).
• Must-have: Ability to work on-site in Westminster, CO.
• Nice-to-have: Experience with UVM, formal verification, FPGA synthesis flows, or prior aerospace/defense experience; security clearance is a plus or may be required.

Education Requirements

The application asks candidates to indicate their highest completed education level (High School / GED, Associate's, Bachelor's, Master's, Doctor of Philosophy (Ph.D.), or J.D.). The posting does not specify a required degree, specific fields of study, certifications, or explicit equivalency language.

About the Company

Company: CesiumAstro

Headquarters: Melbourne, FL, United States

CesiumAstro develops turnkey RF communications and payload systems for satellites, UAVs, launch vehicles, and other space and airborne platforms, providing hardware and software solutions for space communications, signal processing, and on‑orbit data links.