Staff Engineer, Validation/Verification Methodologies (UVM, Simulation, SVA)

Job Title

Staff Engineer, Validation/Verification Methodologies (UVM, Simulation, SVA)

Role Summary

Lead verification efforts for complex IP and SoC designs, focusing on coverage closure using UVM, SystemVerilog Assertions, and simulation tools. Work at the intersection of verification engineering and AI-assisted tooling to improve test generation, debug, and verification productivity.

The role partners with tool and AI teams to validate outputs, shape verification workflows, and build reusable verification knowledge and artifacts across global teams.

Experience Level

Senior. The posting specifies Bachelor's in Electronics with 2+ years of verification experience, or Master's in Electronics with 1+ year of verification experience.

Responsibilities

Accountable for verification strategy, execution, and tooling integration across IP and SoC projects.

• Drive end-to-end verification closure including functional, code, and scenario coverage using UVM, SVA, and simulation.
• Define coverage strategies, identify gaps, and guide convergence to signoff.
• Use and validate AI-assisted tools for testbench generation, coverage analysis, debug, and reporting; independently verify outputs for correctness.
• Ensure verification artifacts (test plans, logs, reports) are well-structured, tagged, and consumable by automated/AI systems.
• Provide actionable feedback to AI/tool development teams to improve models, accuracy, and usability.
• Pilot, benchmark, and measure AI-based verification solutions for productivity and quality impact.
• Contribute to building scalable knowledge systems for reuse across teams and projects.

Requirements

Must-have technical skills and practical verification experience.

• Proven expertise in verification methodologies: UVM, simulation, and SystemVerilog Assertions (SVA).
• Strong understanding of digital design fundamentals using Verilog, VHDL, or SystemVerilog; experience in complex SoC or IP verification environments.
• Hands-on experience with EDA tools such as VCS and Verdi.
• Proficiency in scripting and automation (Python, TCL, UNIX-based workflows).
• Strong debugging and analytical skills; ability to diagnose corner cases and complex verification failures.
• Ability to critically evaluate AI-generated outputs, identify accuracy gaps and edge cases, and provide clear feedback to tool teams.
• Effective communicator capable of working across global teams.
• Nice-to-have: experience or strong interest in AI/ML-assisted verification workflows and data-driven automation.

Education Requirements

Requires a Bachelor's degree in Electronics with 2+ years of verification experience, or a Master's degree in Electronics with 1+ year of verification experience. The posting specifies degrees and years of verification experience; no other degrees, fields, certifications, or explicit "equivalent experience" language were mentioned.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.