Staff Engineer: STA Methodology & Sign-off Lead

Job Title

Staff Engineer: STA Methodology & Sign-off Lead

Role Summary

Lead the architecture and execution of SoC Static Timing Analysis (STA) methodology for sign-off, removing STA bottlenecks and enabling predictable timing closure for large-scale designs. The role bridges Architecture, CAD, RTL, and Physical Design to deliver scalable flows and timing convergence for tape-out.

Experience Level

Senior-level (Staff / Senior Staff). Recommended 8–11 years of hands-on VLSI experience, primarily in STA methodology, flow development, and sign-off at advanced process nodes.

Responsibilities

The lead is expected to define sign-off architecture, build automated flows, qualify tools, and coordinate cross-functional teams to meet aggressive PPA targets.

• Define and own full-chip timing sign-off criteria (MMMC), derate strategies, and operating-condition mappings for functional, shift, and capture modes.
• Architect, deploy, and maintain STA and ECO flows with left-shift automation to find structural timing issues early in RTL/synthesis.
• Establish margin strategies (AOCV, LVF, POCV) and hierarchical vs. flat timing approaches for sign-off.
• Evaluate, qualify, and deploy EDA tool features (strong emphasis on Cadence Tempus) to improve QoR and runtime/memory efficiency.
• Develop scalable automation utilities (Tcl, Python, Perl) for SDC management, timing audits, and ECO acceleration.
• Partner with Physical Design to define CTS and floorplanning guidelines and guide RTL/DFT teams to resolve structural bottlenecks (e.g., NoC timing, complex CDC paths).
• Debug systemic methodology or toolchain issues and drive cross-functional alignment to achieve timing convergence.

Requirements

Must-have technical skills and experience for immediate impact; followed by a short list of desirable skills.

• 8–11 years hands-on VLSI experience with primary focus on STA methodology, flow development, and sign-off at advanced nodes (7nm, 5nm, or below).
• Deep experience building flows around sign-off tools; strong preference for Cadence Tempus expertise.
• Proven mastery of MMMC flow architecture, hierarchical (ILM/ETM) and flat timing strategies, and SDC validation.
• Strong understanding of advanced-node timing phenomena: waveform propagation, crosstalk, and statistical margining (LVF/POCV).
• Proficiency in scripting and automation (Tcl, Python, Perl) to build robust infrastructure and ECO automation.
• Demonstrated ability to architect broad flow solutions and diagnose systemic tool/methodology bottlenecks.
• Leadership and communication skills to define technical standards and influence cross-functional teams.

Nice-to-have:

• Experience optimizing memory/runtime and hierarchical timing models for large SOCs.
• Hands-on experience with clock tree synthesis methodology, floorplanning interactions, or complex NoC timing closure.

Education Requirements

B.Tech or M.Tech in Electrical / Electronics Engineering or a related technical field.

About the Company

Company: EnCharge AI

EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.