Staff Engineer - SoC Power Architecture
QualcommJob Title
Staff Engineer - SoC Power Architecture
Role Summary
Senior engineering role responsible for architecting and optimizing power for next-generation SoCs. Works within Systems Engineering to define SoC-level power features, quantify power/energy impact, and drive cross-functional evaluations with silicon, IP, and validation teams.
Experience Level
Senior - typically requires 8+ years of experience in SoC power architecture, energy management, or low-power design.
Responsibilities
Deliver SoC power-architecture features, evaluate tradeoffs, and validate impacts across silicon and system use-cases.
- Define and evaluate SoC-level power architecture and optimization features across multiple IP blocks and stakeholders.
- Perform energy and latency sensitivity studies for DVFS, clock gating, power gating, and idle/collapse modes.
- Analyze and optimize Vmin margins, power-performance tradeoffs, and silicon robustness.
- Study SOC infrastructure utilization and residency profiles to optimize dynamic and leakage power.
- Develop and validate techniques for voltage droop/overshoot protection, dynamic load-line and PDN management.
- Drive leakage-reduction and low-power strategies across advanced process nodes.
- Create MATLAB models and run SPICE simulations to quantify PPA impacts and support architecture decisions.
- Perform lab characterization and data analysis of power/performance measurements to inform architecture changes.
Requirements
Core technical skills and demonstrated hands-on experience required for success in the role.
- 8+ years of experience in SoC power architecture, energy management, or low-power design.
- Demonstrated expertise in dynamic power optimization, Vmin analysis/margining, and leakage reduction.
- Experience with DVFS, clock gating, power gating, PDN/power-integrity analysis, and power islands.
- Hands-on experience in MATLAB modeling, SPICE simulations, and lab power/performance data analysis.
- Ability to drive cross-functional technical evaluations and communicate tradeoffs to architects and silicon teams.
- Strong analytical skills for quantifying energy/latency sensitivity and residency impacts of use-cases.
- Nice-to-have: experience with advanced process nodes, voltage droop/overshoot mitigation, and dynamic load-line management.
Education Requirements
Bachelor's or Master's degree in Electrical/Electronics Engineering, Engineering, Information Systems, Computer Science, or a related technical field is listed. The posting also specifies alternative combinations of degree and experience: Bachelor's +4+ years, Master's +3+ years, or PhD +2+ years of relevant systems engineering experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
