Staff Engineer, Physical Design

Job Title

Staff Engineer, Physical Design

Role Summary

Lead block-level physical design and methodology for next-generation, high-performance processor/ASIC chips targeting server, networking and 5G/6G applications. Work with a global team to execute place-and-route flows, achieve timing closure, and improve design automation and methodology.

Experience Level

Senior-level. Prefer candidates with 5+ years of hands-on physical design experience on advanced CMOS nodes; additional experience guidance appears in Education Requirements.

Responsibilities

Primary responsibilities include delivering block-level physical implementation and improving the P&R flow and methodology.

• Maintain, enhance, and support the place-and-route flow using industry-standard EDA tools.
• Perform synthesis, placement, routing, and timing analysis/closure for intermediate and complex logic blocks.
• Develop and implement timing and logic ECOs; collaborate with RTL designers to resolve congestion and timing issues.
• Debug and resolve block-level timing issues at the partition level with the global timing team.
• Create and maintain automation scripts to improve design process efficiency.
• Support physical verification and signoff workflows and coordinate with verification teams as needed.

Requirements

Must-have technical skills, tools experience, and personal attributes.

• 5+ years of physical design experience, with a focus on block-level P&R for advanced nodes (7nm, 5nm, or below) preferred.
• Proficiency with physical-design EDA tools such as Cadence Genus and Innovus, and Synopsys IC Compiler or Fusion Compiler.
• Strong experience with static timing analysis tools (Tempus or PrimeTime) and EM/IR analysis tools (Voltus or PrimeRail).
• Ability to create automation scripts (Tcl, Perl, Makefile) to streamline flows and debug issues.
• Effective communicator, detail-oriented, and able to work collaboratively across global teams.
• Awareness that the role may require export-control eligibility and related export-license reviews.
• Nice-to-have: experience with physical and formal verification tools (Calibre, LEC, Formality) or prior methodology development roles.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with approximately 3–5 years of related professional experience; or a Master’s degree or PhD in Computer Science, Electrical Engineering, or related fields with approximately 2–3 years of related experience. Equivalent professional experience in lieu of a formal degree is explicitly accepted.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.