Staff Engineer, Physical Design - Caches

Job Title

Staff Engineer, Physical Design - Caches

Role Summary

Lead the physical implementation of cache blocks and tightly integrated SRAM subsystems from RTL to GDSII. Work across architecture, RTL, and implementation teams to deliver high-performance, dense, and power-efficient memory designs.

Primary responsibility is to optimize Power, Performance, and Area (PPA) for memory subsystems and ensure reliable integration of memory instances into SoC designs.

Experience Level

Senior — typically 7+ years of relevant physical design experience, particularly on PPA-critical blocks such as CPUs and caches.

Responsibilities

The role owns implementation and cross-layer optimization for cache and memory subsystems.

• Lead physical design implementation for cache blocks and SRAM subsystems: synthesis, place & route, and signoff.
• Participate in architecture/RTL/implementation co-design to resolve physical bottlenecks and improve micro-architecture/implementation trade-offs.
• Address memory-specific challenges: dense SRAM macro placement, routing over macros, and timing through memory arrays.
• Optimize block-level PPA trade-offs across product lines.
• Collaborate with RTL designers, IP vendors, and power teams to close requirements and ensure efficient integration.
• Improve physical design flows, automation scripts, and methodologies for memory-heavy implementations.

Requirements

Required skills and experience.

• Must have: 7+ years hands-on experience implementing PPA-critical blocks (CPUs, caches, memory subsystems).
• Must have: Strong understanding of digital logic and memory architecture; ability to read RTL and collaborate with front-end teams.
• Must have: Proven problem-solving ability to meet aggressive PPA targets using industry-standard physical design techniques.
• Must have: Hands-on experience with RTL-to-GDSII implementation flows using Synopsys and/or Cadence tools for synthesis, place & route, and signoff.
• Must have: Good scripting skills for automation (e.g., Python, TCL, Perl, or similar).
• Nice to have: Experience with dense SRAM macro integration, advanced process nodes, and cache microarchitecture-oriented optimizations.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.