Staff Engineer - Physical Design and Signoff (Synthesis to GDS2)
SynopsysRole Summary
The Staff Engineer in Physical Design and Signoff will be responsible for conceptualizing, designing, and productizing advanced RTL to GDS implementation using ASIC design methodologies. This role involves executing various digital backend activities and collaborating with engineers to refine process flows.
Experience Level
Mid-level, with a minimum of 5 years of relevant industry experience required.
Responsibilities
The key responsibilities for this role include:
- Conceptualizing and designing state-of-the-art RTL to GDS implementations.
- Designing on-chip monitors for silicon biometrics and reliability.
- Executing digital backend activities, including synthesis and floor planning.
- Driving post-layout STA and timing signoff for high-frequency designs.
- Performing physical verification tasks and ensuring compliance with reliability standards.
- Collaborating with architects and circuit design teams to enhance methodologies.
Requirements
Must-have skills and experience:
- BS/B.Tech or MS/M.Tech in Electrical Engineering.
- 5+ years in Physical Design and Verification, including STA and power signoff.
- Hands-on experience with DRC, LVS, and timing closure.
- Proficiency in using EDA tools, specifically those from Synopsys.
- Experience with advanced technology nodes (14nm to 2nm).
Education Requirements
BS/B.Tech or MS/M.Tech in Electrical Engineering is required.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
