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Senior/ Staff STA Engineer

Renesas
April 23, 2026
Remote friendly (Bengaluru, Karnataka, India)
Worldwide
Level - Mid-Career

Job Title

Senior/ Staff STA Engineer

Role Summary

The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with various teams to debug violations and drive ECO-based optimizations through tapeout.

Experience Level

Mid-level; 4–12 years of experience in Static Timing Analysis (STA) and timing closure.

Responsibilities

Key responsibilities include:

  • Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
  • Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
  • Collaborate with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
  • Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
  • Drive timing closure through ECO implementation and timing optimization.
  • Analyze timing impact due to process, voltage, and temperature variations.
  • Support timing signoff for pre-layout and post-layout stages.
  • Perform cross-functional reviews for timing convergence and provide recommendations.
  • Generate timing reports and communicate closure status to project stakeholders.

Requirements

The desired qualifications are:

  • Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
  • Hands-on experience with setup/hold analysis, and various timing violations.
  • Experience with timing constraints development and debugging.
  • Familiarity with timing closure techniques and ECO methodologies.
  • Knowledge of SDC and timing exceptions
  • Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
  • Good scripting skills in Tcl, Perl, or Python.
  • Ability to analyze and resolve timing violations independently.

Education Requirements

Not specified.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-04-23