Staff Engineer - Physical Design
SynopsysJob Title
Staff Engineer - Physical Design
Role Summary
Lead physical implementation of UCIe PHY blocks and associated testchips from floorplan through tapeout on advanced process nodes. Work across synthesis, P&R, timing closure and physical verification to deliver production-quality IP and test silicon.
Experience Level
Senior — the role is senior-level. The posting requests approximately 4 to 7 years of hands-on ASIC physical design experience.
Responsibilities
Accountable for physical design delivery, tradeoffs, and mentoring on multiple concurrent projects.
- Own physical implementation of UCIe PHY blocks and testchips from floorplanning through GDS/tapeout on 5nm and more advanced nodes.
- Drive synthesis, place & route, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV.
- Collaborate with verification, DFT, and IP integration teams to resolve issues and meet PPA and schedule targets.
- Lead design reviews, present tradeoff analyses, and make real-time floorplan/CTO/signoff decisions.
- Pilot and document new physical design flows and advanced-node methodologies for team adoption.
- Mentor junior engineers on timing closure, physical verification, and ICC2 toolchain usage.
- Interface with foundry partners and customer engineering teams to resolve technology-file, DRC/LVS, and silicon bring-up issues.
Requirements
Must-have technical experience and skills for immediate contribution.
- 4–7 years of hands-on ASIC physical design experience, including synthesis, P&R, timing closure, and physical verification.
- Multiple tapeouts and signoffs at 5nm or more advanced nodes; experience taking designs to GDS.
- Proficiency with industry tools: Design Compiler (DC), PrimeTime (PT), ICC2/Foundry Compiler (FC), and ICV or equivalent physical verification tools.
- Proven ownership on SoC or IP tapeouts with accountability for physical signoff.
- Strong understanding of FinFET challenges at advanced nodes (multi-patterning, electromigration, IR drop).
- Ability to prioritize timing vs. area tradeoffs and make decisions under schedule pressure.
Nice-to-have:
- Experience with DFT insertion, scan chain routing, and ATPG; experience debugging DFT-related timing/physical issues.
- Exposure to UCIe, SerDes, or other high-speed interface IP.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
