Staff Engineer, Physical Design

Job Title

Staff Engineer, Physical Design

Role Summary

Lead block- and subsystem-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. Collaborate with SoC teams to align clocking, floorplanning intent, and integration requirements while improving subsystem methodologies and automation. Position is based in Bengaluru.

Experience Level

Senior-level; requires 8+ years of physical design experience focused on subsystem-level closure for complex SoCs.

Responsibilities

Primary responsibilities include:

• Lead block- and subsystem-level physical design closure: timing closure, congestion mitigation, power integrity, and implementation quality.
• Collaborate with SoC physical design teams to align clocking strategies, floorplanning intent, and integration requirements without owning SoC-level execution.
• Apply clocking methodologies to ensure subsystem clock domains integrate into the broader SoC clock architecture.
• Develop, refine, and scale subsystem closure methodologies, flows, and automation to improve predictability and execution efficiency.
• Mentor and guide physical design engineers on best practices and methodology adoption.
• Work cross-functionally with RTL, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure.
• Identify, assess, and mitigate physical design risks and coordinate with SoC teams to drive technical solutions.

Requirements

Must-have technical skills and experience:

• 8+ years of physical design experience with subsystem-level closure for hierarchical SoCs.
• Expertise in timing closure and constraint management.
• Experience in congestion analysis and resolution.
• Knowledge of power integrity and power-aware physical implementation.
• Understanding of SoC-level floorplanning and clocking methodologies (clock domain partitioning, clock tree architecture, skew management, clock gating).
• Hands-on experience with Synopsys (ICC2, Fusion Compiler, PrimeTime) and Cadence (Innovus, Tempus, Certus) tool flows and signoff/analysis platforms.
• Proficiency in scripting and automation using Tcl, Python, and/or Perl.
• Strong collaboration experience across timing, power, clocking, verification, and backend teams.
• Familiarity with low-power design techniques and power-aware implementation methodologies.

Education Requirements

B.Tech or M.Tech in Electronics and Communication, Electrical Engineering, Computer Science, or a related field.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.