Staff Engineer, NPU/AI Processor Synthesis (Design Implementation)
QualcommJob Title
Staff Engineer, NPU/AI Processor Synthesis (Design Implementation)
Role Summary
Drive RTL-to-GDS synthesis and timing closure for NPU/AI accelerator IP and subsystems on advanced process nodes. Work within the SoC implementation team and partner with Architecture, RTL, STA, DFT, and Physical Design to meet PPA and tapeout goals.
Experience Level
Senior level - Staff Engineer. Typical experience range for this level: approximately 8–12 years of relevant ASIC/SoC implementation experience; specific seniority may vary by hiring band.
Responsibilities
Primary responsibilities focus on synthesis, timing closure, and flow automation for complex hierarchical designs.
- Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.
- Develop and maintain synthesis flows, constraints (SDC), and automation for hierarchical designs.
- Drive pre-layout and post-layout timing closure across modes and process corners.
- Optimize designs for performance, power, and area using physical-aware synthesis methods.
- Create and validate clock definitions, false paths, and multi-cycle paths; maintain SDCs.
- Collaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.
- Perform quality checks including LEC, CDC, lint, and low-power verification.
- Analyze and improve synthesis QoR through scripting and flow enhancements.
- Support tapeout activities and drive continuous improvements in synthesis methodologies.
Requirements
Must-have technical skills and experience required for successful performance in this role.
- Strong understanding of the ASIC design flow from RTL to GDS and hands-on experience with RTL synthesis and timing closure.
- Practical experience with Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
- Timing analysis expertise using PrimeTime or equivalent STA tools.
- Experience with low-power design methodologies and UPF-based flows.
- Good understanding of clocking architecture, timing constraints, and timing signoff.
- Proficiency in TCL and scripting (Python, Perl, or similar) for flow automation and QoR improvement.
- Strong debugging, problem-solving, and cross-functional collaboration skills.
Nice-to-have
- Experience on AI/ML accelerators (NPU), DSP, GPU, CPU, or other high-performance compute architectures.
- Knowledge of advanced process nodes (5nm, 4nm, 3nm and below).
- Experience with physical-aware synthesis and hierarchical design methodologies.
- Familiarity with LEC, CDC, lint, power analysis, and low-power verification flows.
- Proven track record of successful SoC or IP tapeouts.
Education Requirements
Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related technical field. The posting specifies degree-plus-experience alternatives: Bachelor's with 4+ years, Master's with 3+ years, or PhD with 2+ years of relevant hardware engineering or related experience (equivalent practical experience considered per those combinations).
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
