Staff Engineer, Low Power Verification & Formal Equivalence

Job Title

Staff Engineer, Low Power Verification & Formal Equivalence

Role Summary

Lead low-power verification and formal equivalence signoff methodologies for advanced SoC/ASIC designs. Own static low-power checks, UPF strategy/automation, and logical equivalence flows from RTL through post-route while partnering with Physical Design and Power teams.

Work will focus on ensuring robust power intent implementation and flawless logical equivalence for high-performance RISC-V designs.

Experience Level

Senior — the posting specifies 7+ years of relevant industry experience in ASIC/SoC design and verification.

Responsibilities

Core responsibilities and ownership areas for this role:

• Own static low-power verification checks across the design hierarchy and ensure coverage and correctness.
• Architect, optimize, and automate UPF (Unified Power Format) coding and deployment with Platform Engineering and Power architects.
• Lead Formal Equivalence Checking (LEC) and formal signoff flows, ensuring logical equivalence from RTL through post-route and managing ECO implementations.
• Coordinate closely with Physical Design and Power teams to produce implementable, optimized UPF and equivalence solutions.
• Drive tooling and methodology improvements for low-power signoff and formal ECO flows.

Requirements

Must-have technical skills and experience (degree and specific years moved to Education Requirements):

• Authoritative experience architecting and coding power intent using UPF, including automation of UPF flows.
• Proven expertise running, analyzing, and debugging static low-power checks on RTL and post-PNR netlists using industry-standard tools (example: Synopsys VC Low Power / VCLP).
• Extensive hands-on experience with Logical Equivalence Checking and formal equivalence tools and driving formal ECO flows (example: Synopsys Formality).
• Technical knowledge of power-management library cells and their physical/logical implications, including isolation cells, level shifters, AON cells, and retention registers.
• Experience coordinating cross-functional teams and managing complex, late-stage engineering changes (ECOs).

Nice-to-have:

• Foundational knowledge of backend Physical Design (PD) flow to anticipate implementation challenges.
• Scripting and automation skills (Tcl, Python, or Perl) to build and maintain automated flows and custom rules.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. The posting specifies 7+ years of relevant industry experience in ASIC/SoC design and verification.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.