Silicon Labs logo

Staff Engineer - IC Design

Silicon Labs
August 11, 2026
Full-time
On-site
Hyderabad, Telangana, India
RTL Design Jobs, Level - Senior

Job Title

Staff Engineer - IC Design

Role Summary

Design and deliver synthesizable RTL and digital IP for SoC integration, focusing on architecture, micro-architecture, and reusable IP development. Work with verification, synthesis, and integration teams to meet performance, power, and area (PPA) targets through tape-out and post-silicon bring-up.

Experience Level

Senior β€” 5–15 years of experience in RTL design and digital IP development.

Responsibilities

Primary responsibilities include end-to-end IP design, integration support, and mentoring.

  • Develop synthesizable RTL (Verilog/SystemVerilog) for digital IP blocks.
  • Drive IP development from specification through tape-out and support post-silicon validation and debug.
  • Ensure designs meet PPA targets and support timing closure activities.
  • Produce and maintain micro-architecture specs, design specs, and integration guides.
  • Collaborate with verification teams to develop test plans and resolve functional issues.
  • Support synthesis, lint, CDC/RDC analysis, and gate-level debugging.
  • Work closely with SoC integration teams for IP integration and bring-up.
  • Contribute to IP reuse, configurability, design methodology improvements, and mentor junior engineers.

Requirements

Minimum technical qualifications and relevant skills.

Must-have:

  • 5–15 years of experience in RTL design and digital IP development.
  • Strong proficiency in Verilog/SystemVerilog.
  • Solid understanding of digital design fundamentals, FSM and datapath design, pipelining, and performance optimization.
  • Experience with clock domain crossing (CDC) and reset domain crossing (RDC), and low-power design concepts.
  • Experience with synthesis and timing analysis; familiarity with industry-standard EDA tools (Synopsys/Cadence/Mentor).
  • Strong RTL and gate-level debugging skills.
  • Experience with AMBA protocols (AXI/AHB/APB).

Preferred / Nice-to-have:

  • Experience developing peripheral IP (SPI, UART, I2C/I3C, DMA controllers, timers, interrupt controllers, memory controllers).
  • Exposure to wireless subsystems, preferably Wi‑Fi (IEEE 802.11) or MAC-level architecture.
  • Experience with packet processing or high-speed datapath design, security/crypto IP, scripting (Python/Perl/TCL), and advanced technology nodes.
  • Familiarity with AI-powered productivity tools is a plus.

Education Requirements

Bachelor's or Master's degree in Electronics/Electrical Engineering or a related field.


About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.

Silicon Labs logo

Date Posted: 2026-08-10