Staff Engineer – DFT Engineering

Job Title

Staff Engineer 6 DFT Engineering

Role Summary

Join the VLSI design team to lead design-for-testability (DFT) implementation and validation across complex ASICs. The role focuses on enabling manufacturing testability, delivering ATPG/MBIST patterns, and ensuring DFT structures are verified in RTL and netlist stages.

The position requires close collaboration with design, verification, physical design and test teams to define DFT strategies and resolve test failures.

Experience Level

Senior (Staff) level. Typically 7 610 years of hands-on experience in DFT methodologies and ASIC test flow.

Responsibilities

Primary duties include design, validation, and support of DFT features and test deliverables.

• Design and implement DFT features such as scan chains, compression, LBIST, and MBIST to improve testability.
• Generate high-quality manufacturing ATPG patterns for stuck-at and transition faults using on-chip compression techniques.
• Perform DFT DRC checks in RTL and netlist databases to ensure compliance with DFT rules.
• Validate DFT structures and patterns in RTL and netlist with and without SDF timing.
• Collaborate with verification, physical design, and test teams to define verification plans, synthesis/STA constraints, and debug test failures.
• Use EDA DFT tools to analyze and optimize testability and coverage metrics.
• Provide guidance and mentorship to junior DFT engineers.
• Travel as required for cross-site collaboration (approximately 10% of the time).

Requirements

Must-have technical skills and experience.

• 7 610 years of hands-on experience in DFT methodologies and techniques.
• Strong practical knowledge of LBIST, ATPG, DFT DRC, scan compression, low-power DFT techniques, MBIST, boundary scan, analog DFT, and JTAG architecture.
• Hands-on experience with Cadence and Siemens DFT EDA tools for scan stitching, DRC, ATPG, coverage improvement, MBIST, and boundary scan.
• Proficiency in scripting for automation (Perl, Tcl, and/or Python).
• Solid understanding of digital design fundamentals including RTL coding, Lint/CDC checks, low-power checks, and standard ASIC design flow.
• Experience defining DFT STA constraints and working with physical design for DFT implementation.
• Ability to analyze and debug test failures and collaborate with cross-functional teams to resolve issues.
• Strong problem-solving, communication, and mentoring skills.

Education Requirements

Bachelor's or Master's degree in Electrical or Electronic Engineering or a related field.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.