Staff Engineer, Design Verification Engineering

Job Title

Staff Engineer, Design Verification Engineering

Role Summary

Lead pre-silicon design verification for complex SoC and subsystem products. The role defines verification architecture, flows and methodology, drives verification execution to closure, and coordinates across emulation, FPGA, firmware and design teams.

This position is part of Analog Devices' digital design verification organization focused on high-performance integrated products for edge intelligence.

Experience Level

Senior — 8+ years experience in digital pre-silicon verification.

Responsibilities

Primary responsibilities include planning and executing verification for large integrated products and improving verification methodology across teams.

• Lead pre-silicon verification activities from planning through closure for complex SoC or subsystem designs.
• Architect and implement UVM-based testbenches, DV flows and scalable verification environments.
• Define and execute test plans; drive functional and code coverage closure in collaboration with design teams.
• Verify microprocessor-based systems, AI/ML accelerators and high-speed peripherals.
• Coordinate with emulation, FPGA and firmware teams for end-to-end system validation.
• Apply formal verification techniques for IP and subsystem validation.
• Lead NoC/interconnect verification and validate system data flow and connectivity.
• Perform system-level use-case validation, performance verification and analysis.
• Develop and validate end-to-end scenarios to ensure real-world functionality.
• Define overall verification strategy leveraging formal, emulation, portable stimulus and virtual platform techniques.

Requirements

Must-have technical skills and experience to perform the role; Nice-to-have items listed separately.

Must-have:

• 8+ years of experience in digital pre-silicon verification.
• Strong understanding of SoC and subsystem architectures.
• Hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven experience achieving verification closure using functional and code coverage metrics at block and subsystem levels.
• Experience with NoC, bus and interconnect verification, including coverage analysis and optimization.
• Experience architecting testbench environments and implementing scalable DV flows and methodologies.
• Hands-on power-aware verification experience using UPF, including power analysis and optimization.
• Exposure to formal verification and familiarity with gate-level simulations (timing annotated GLS).
• Knowledge of test planning, constrained-random verification, assertions and transaction-level modeling in SystemVerilog.
• Proficiency in C/C++, SystemC and scripting (Python, TCL, Shell).
• Strong communication and collaboration skills; ability to work across global teams.
• Willingness to travel (~10%).

Nice-to-have:

• Familiarity with processor-based systems (ARM, RISC-V, Tensilica) and AI/ML or GPU-based architectures.
• Experience with emulation, FPGA-based validation and portable stimulus approaches.
• Track record of technical leadership, patents or publications.

Education Requirements

B.Tech or M.Tech degree (as listed in the source posting).

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.