Staff Engineer, Design Verification Engineering

Job Title

Staff Engineer, Design Verification Engineering

Role Summary

Lead pre-silicon design verification for complex SoC and subsystem products within a multifunctional engineering team. Define verification architecture, methodology and flows, and drive verification activities from planning through closure.

Work cross-functionally with emulation, FPGA, firmware and design teams to ensure end-to-end system correctness and to influence verification methodology across business units.

Experience Level

Senior — typically 8+ years of experience in digital pre-silicon verification.

Responsibilities

Primary responsibilities include:

• Lead pre-silicon verification for complex SoC or subsystem designs, driving execution from planning to closure.
• Architect and implement UVM-based testbenches, DV flows, and scalable verification methodologies.
• Verify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals.
• Define and execute test plans; drive functional and code coverage closure in collaboration with design teams.
• Work with emulation, FPGA, and firmware teams for end-to-end system validation.
• Apply formal verification techniques for IP and subsystem validation.
• Lead NoC/interconnect verification, including coverage analysis and optimization.
• Perform system-level use-case validation and performance verification; develop end-to-end scenarios for real-world functionality.
• Implement power-aware verification and participate in power analysis and optimization.
• Mentor peers and influence verification methodologies across teams.

Requirements

Must-have skills and experience:

• 8+ years of experience in digital pre-silicon verification.
• Hands-on expertise with Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven experience achieving verification closure using functional and code coverage metrics at block and subsystem levels.
• Experience with NoC, bus, and interconnect verification, including coverage analysis and optimization.
• Experience architecting testbench environments and implementing scalable DV flows and methodologies.
• Power-aware verification experience (UPF) and related power analysis.
• Exposure to formal verification and gate-level simulation with timing annotation.
• Proficiency in C/C++, SystemC, and scripting (Python, TCL, Shell).
• Strong communication and collaboration skills; ability to work across global teams.
• Willingness to travel approximately 10% of the time.

Nice-to-have:

• Familiarity with processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures.

Education Requirements

B.Tech or M.Tech degree required (as stated in the posting). No specific field of study, certifications, or equivalent-experience language were specified in the job text.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.