Staff Engineer, Design Verification Engineering

Job Title

Staff Engineer, Design Verification Engineering

Role Summary

Senior member of the pre-silicon design verification team responsible for planning, architecting and executing verification for complex SoC and subsystem designs. The role partners with design, emulation, FPGA, and firmware teams to deliver functional and system-level correctness.

Experience Level

Senior — 8+ years of experience in digital pre-silicon verification.

Responsibilities

Primary responsibilities focus on verification strategy, implementation, and closure for large integrated products.

• Lead pre-silicon verification for complex SoC or subsystem designs from planning to closure.
• Architect and implement UVM-based testbenches, DV flows, and scalable verification methodologies.
• Define and execute test plans; drive functional and code coverage closure in collaboration with design teams.
• Verify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals.
• Work cross-functionally with emulation, FPGA, and firmware teams for end-to-end validation.
• Apply formal verification techniques and perform NoC/interconnect verification.
• Perform system-level use-case validation, performance verification and analysis.
• Develop and validate end-to-end scenarios and drive verification innovation to meet quality and schedule targets.

Requirements

Must-have technical skills and experience to perform the role; nice-to-have items listed separately.

• Must-have: Strong hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven experience achieving verification closure using functional and code coverage metrics at block and subsystem levels.
• Expertise in NoC, bus, and interconnect verification, including coverage analysis and optimization.
• Experience architecting testbench environments and implementing scalable DV flows and methodologies.
• Hands-on experience in power-aware verification using UPF, including power analysis and optimization.
• Exposure to formal verification and familiarity with gate-level simulations with timing annotation.
• Strong knowledge of test planning, constrained-random verification, assertions, and transaction-level modeling.
• Proficiency in C/C++, SystemC and scripting (Python, TCL, Shell).
• Excellent communication and collaboration skills; ability to work across global teams.
• Willingness to travel up to 10%.
• Nice-to-have: Familiarity with processor architectures (ARM, RISC-V, Tensilica), AI/ML or GPU-based architectures; experience with emulation, portable stimulus, or virtual platforms.

Education Requirements

B.Tech or M.Tech degree specified. The posting requests 8+ years of experience in digital pre-silicon verification.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.