Staff Engineer, Design Verification Engineering

Job Title

Staff Engineer, Design Verification Engineering

Role Summary

Lead pre-silicon design verification for complex SoC and subsystem products. Responsible for verification strategy, architecture, methodology, and driving closure across block, subsystem and system levels.

Work in a multifunctional team engaging with emulation, FPGA, firmware and design groups to ensure end-to-end correctness and delivery. Travel required up to 10%.

Experience Level

Senior — 8+ years of experience in digital pre-silicon verification.

Responsibilities

Key responsibilities include planning and executing verification for large integrated products and ensuring functional and code coverage closure.

• Lead pre-silicon verification from planning through closure for SoC or subsystem designs.
• Architect and implement UVM-based testbenches, DV flows, and scalable methodologies.
• Define and execute test plans; drive functional and code coverage closure with design teams.
• Verify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals.
• Collaborate with emulation, FPGA, and firmware teams for end-to-end validation.
• Apply formal verification techniques and perform NoC/interconnect verification.
• Perform system-level use case validation, performance verification, and analysis.
• Develop end-to-end scenarios to validate real-world functionality and meet schedule and quality goals.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Strong understanding of SoC and subsystem architectures; hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven experience achieving verification closure using functional and code coverage metrics at block and subsystem levels.
• Expertise in NoC, bus, and interconnect verification, including coverage analysis and optimization.
• Experience architecting testbench environments and implementing scalable DV flows and methodologies.
• Hands-on experience in power-aware verification using UPF, including power analysis and optimization.
• Exposure to formal verification, including flow setup and functional checks.
• Familiarity with gate-level simulations (GLS) and timing annotation.
• Strong test planning skills; constrained-random verification, assertions, and transaction-level modeling.
• Proficiency in C/C++, SystemC, and scripting (Python, TCL, Shell).
• Excellent communication and collaboration skills; ability to work across global teams and influence verification methodology adoption.
• Willingness to travel up to 10% as required.

Education Requirements

B.Tech or M.Tech degree. The posting specifies 8+ years of experience in digital pre-silicon verification. Fields of study are not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.