Staff Engineer, Design Verification
Responsible for verification and evaluation of digital circuits in high-speed data communication ICs within Central Engineering's verification and AMS-IP teams. Work focuses on block- and chip-level verification for PCIe, Ethernet and SerDes PHY to support SoC production and lab validation.
Collaborate with lab validation, system engineering, and cross-functional design teams to deliver coverage-driven verification environments, models, and automated flows.
Senior — typically a Bachelor’s degree plus 7–8 years of related experience, or a Master’s/PhD plus 5–6 years of related experience.
Primary responsibilities include verification planning, environment development, test execution, mixed-signal validation, and cross-team collaboration.
Key technical requirements and skills.
Bachelor’s degree in Computer Science, Electrical Engineering or a related field with 7–8 years of relevant professional experience; or a Master’s degree or PhD in these fields with 5–6 years of relevant experience. Related technical degrees are acceptable.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
