Staff Engineer, ASIC/VLSI Synthesis and Design

Job Title

Staff Engineer, ASIC/VLSI Synthesis and Design

Role Summary

Lead synthesis and front-end implementation activities for complex SoC and block-level designs, focusing on timing-constraint development, logic synthesis, timing closure, and handoff to place-and-route and physical design teams. Work within cross-functional teams (Architecture, RTL, DFT, Analog, PD) to ensure designs meet performance, power, and area targets.

This role may require access to export-controlled technology; candidates must be eligible for export-controlled information as defined by applicable law.

Experience Level

Senior-level (Staff). The posting indicates multiple years of ASIC/synthesis experience; expect senior responsibility for flow ownership and mentoring.

Responsibilities

Primary responsibilities include ownership of front-end synthesis and timing tasks and collaboration with cross-functional teams.

• Develop and validate timing constraints for complex SoC and hierarchical designs.
• Maintain and execute synthesis, logical equivalence checks (LEC/LEQ), and functional ECO flows.
• Perform physical-aware synthesis and timing-driven optimizations using industry tools (e.g., Fusion Compiler).
• Collaborate with Architecture, RTL, DFT, Analog, and Physical Design teams to create consolidated timing modes and budgets for synthesis, PnR and chip sign-off.
• Drive timing analysis (STA), timing closure, and tradeoffs across power/performance/area.
• Develop and validate UPF for blocks and SoCs; perform UPF validation with industry tools.
• Automate front-end flows and processes with scripting (Tcl, Python, etc.).
• Investigate and resolve EDA tool issues, working independently or with vendors.
• Ensure netlist handoff criteria are met and document best practices to improve future projects.

Requirements

Must-have technical skills and experience to perform the role effectively.

• Hands-on experience with logic synthesis flows, STA methodologies, and front-end implementation for high-speed designs.
• Experience with timing constraint development for hierarchical designs and timing budgeting.
• Proficiency in synthesis and STA tools and practical use of industry flows for LEC, ECO, and sign-off.
• Experience with physical-aware synthesis and timing optimization techniques to achieve closure.
• Practical scripting skills for automation (Tcl, Python; Perl familiarity is beneficial).
• Experience with UPF development and UPF validation flows and tools.
• Proven ability to analyze power/performance/area tradeoffs and deliver to schedule.
• Strong problem-solving, debugging, and communication skills for cross-functional collaboration.
• Minimum of 1 year of industry experience in ASIC implementation and synthesis.
• Nice-to-have: experience with Fusion Compiler, Conformal ECO/LEC, Conformal Low Power; prior work on advanced nodes (TSMC N4/N5) and high-complexity silicon.

Education Requirements

Required: Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 3–5 years of related professional experience; OR Master’s degree or PhD in Computer Science, Electrical Engineering, or related field with 2–3 years of related experience. Equivalent practical experience in lieu of degree is implied by the stated degree-or-experience options.

For reasonable accommodation during the selection process, contact Marvell HR Helpdesk at TAOps@marvell.com.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.