Staff Engineer, ASIC IP STA

Job Title

Staff Engineer, ASIC IP STA

Role Summary

Member of the AMS IP Physical Design team responsible for post-layout static timing analysis (STA) signoff and timing closure of high-speed interface IPs (memory and IO PHYs). Works closely with IP design, SoC synthesis, and SoC physical design teams through IP development and SoC integration.

Experience Level

Senior level. Typical experience: 6–10 years in STA with demonstrated tapeout experience.

Responsibilities

Deliver timing signoff and closure for high-speed interface IPs and provide timing collateral for SoC integration.

• Perform post-layout STA signoff and timing closure for DDR PHY, ONFI PHY, IO Expander, or similar IPs.
• Develop, validate, and debug timing constraints including clocks, generated clocks, timing exceptions, and mode-specific constraints.
• Run MMMC timing analysis and closure across functional, scan, MBIST, and DFT modes.
• Produce and validate timing models (Liberty/.lib and ETM) and early timing collateral to support SoC integration.
• Generate and validate SDF, support gate-level simulation (GLS) for verification teams.
• Apply SI-aware timing signoff methods (OCV/AOCV/POCV), setup/hold, recovery/removal, and pulse-width checks.
• Automate timing flows and analysis using TCL and/or Python; support methodology development.
• Coordinate across cross-functional teams to drive timing closure and resolve issues.

Requirements

Must-have technical skills and proven deliverables.

• 6–10 years of STA experience with a track record of multiple successful tapeouts (4+ preferred).
• Hands-on experience with Cadence Tempus (preferred) and familiarity with Genus and Innovus flows.
• Expertise in MMMC timing analysis and closure across functional, scan, MBIST, and DFT modes.
• Experience on high-speed memory/interface IPs such as DDR PHY, ONFI PHY, or IO Expander.
• Ability to generate and validate Liberty (.lib) and ETM timing models and assess timing model quality.
• Experience with SDF generation, validation, and gate-level simulation support.
• Strong understanding of OCV/AOCV/POCV methodologies, setup/hold, recovery/removal, and pulse-width checks.
• Proficiency in TCL and/or Python for automation and timing methodology development.
• Strong analytical, debugging, communication, and stakeholder-management skills.

Nice-to-have:

• Experience with advanced-node, high-frequency designs (LPDDR/DDR, ONFI, IO Expander).
• Exposure to AMS/Digital-on-Top integration flows and mixed-signal timing signoff challenges.
• Familiarity with AI/ML-enabled EDA methodologies and AI-assisted timing workflows.

Education Requirements

Bachelor's (BE/B.Tech) or Master's (M.Tech) degree in Electrical/Electronics Engineering, ECE, VLSI, Micron Electronics, or a closely related technical field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.