Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

Job Title

Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

Role Summary

Senior timing/STA engineer responsible for timing constraint development, static timing analysis (STA) signoff flows, timing ECOs, and timing closure for complex SoC and block-level designs. Works with architecture, RTL, DFT, analog, and physical teams to define and deliver timing signoff for advanced-node silicon and chiplet/interconnect designs.

This role supports high-performance data-center interconnect and Photonic Fabric technologies and may require eligibility to access export-controlled technology.

Experience Level

Senior. Typical experience described: Bachelor’s + 3–5 years, or Master’s/PhD + 2–3 years; minimum of 1 year industry ASIC timing/STA experience required.

Responsibilities

Deliver STA and timing signoff processes for blocks and SoCs; automate and document flows to ensure repeatable, high-quality results.

• Develop and validate timing constraints and consolidated timing modes for hierarchical SoC designs.
• Run STA signoff flows, perform post-route timing checks and QoR analysis.
• Create and manage timing ECOs and timing budgets to achieve closure.
• Define signoff methodologies (process corners, derates, uncertainties) and ensure checklist compliance.
• Automate STA processes and dashboards using scripting (Tcl, Python, etc.).
• Analyze timing results, generate histograms/QoR reports, and document lessons learned and best practices.
• Resolve tool issues independently or with EDA vendors.

Requirements

Must-have technical skills and experience; listed as concise requirements. Degrees and formal academic requirements are summarized separately under Education Requirements.

• Minimum of 1 year of industry ASIC timing/STA experience.
• Strong understanding of ASIC design flows from RTL to GDSII.
• Hands-on experience with STA methodologies and implementation.
• Proficiency with STA tools (e.g., Primetime) and scripting languages (Tcl, Python, Perl).
• Experience developing timing constraints for hierarchical designs, timing ECO creation, and timing signoff.
• Familiarity with physical design and timing optimization techniques for deterministic closure.
• Experience with advanced technology nodes; TSMC N4/N5 preferred.
• Strong problem-solving skills, attention to detail, and ability to collaborate cross-functionally.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 3–5 years of related professional experience; OR Master’s degree or PhD in Computer Science, Electrical Engineering, or related fields with 2–3 years of related experience. (Degrees and field-of-study are specifically requested in the posting.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.