Staff Engineer, AMS Verification

Job Title

Staff Engineer, AMS Verification

Role Summary

Lead verification of digital content embedded in power, analog, and mixed-signal IC products. Senior individual-contributor responsible for verification architecture, methodology, execution, and sign-off at block and full-chip levels.

Experience Level

Senior - typically requires 10+ years of AMS verification experience.

Responsibilities

Primary responsibilities include:

• Own block-level and full-chip digital verification strategy and drive verification sign-off for power, analog, and mixed-signal products.
• Develop verification plans from product and design specifications: feature extraction, test intent, coverage goals, assumptions, and sign-off criteria.
• Design and implement SystemVerilog/UVM testbenches, agents, scoreboards, assertions, sequences, reference models, and coverage models.
• Set up and run verification flows and regressions; perform triage, debug, closure, and provide clear evidence of design correctness before tape-out.
• Apply simulation, assertion-based verification, formal verification, and FPGA/emulation where appropriate.
• Verify digital behavior across reset, clock, power-state, fault, trim, communication, test-mode, and analog-interaction scenarios.
• Collaborate with analog and digital teams on models and abstraction levels; support gate-level, timing-aware, and post-layout verification and silicon bring-up.
• Drive reusable methodology, automation, metrics, documentation, mentor engineers, and provide status/coverage/risk/sign-off assessments.

Requirements

Must-have skills and experience:

• Extensive hands-on experience with SystemVerilog and UVM for testbench and environment development.
• Proven ownership of block-level and full-chip verification environments and sign-off for complex semiconductor products.
• Strong knowledge of functional verification, assertion-based verification, formal verification, regression frameworks, coverage closure, and debug methodologies.
• Experience verifying digital logic embedded in PMICs, power-management, automotive, audio, or other mixed-signal ICs.
• Good understanding of RTL, microarchitecture, clocks, resets, low-power states, register interfaces, and common serial interfaces such as SPI, I2C, or UART.
• Working knowledge of synthesis, static timing analysis (STA), DFT, scan insertion, ATPG, and gate-level verification to collaborate across the development flow.
• Scripting and automation skills using Python, TCL, Perl, shell, or similar languages.
• Proven ability to mentor engineers, establish verification methodology, lead technical reviews, and deliver under tight schedules in multisite and multicultural teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical discipline.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.