Staff Digital Verification Engineer – UVM/SystemVerilog

Job Title

Staff Digital Verification Engineer – UVM/SystemVerilog

Role Summary

Lead development of SystemVerilog/UVM verification environments for high-speed PHYs, controllers and chiplets at an early-stage startup. Work with cross-functional teams to define verification strategy, drive testbench and regression infrastructure, and mentor junior engineers.

Experience Level

Senior-level; posting requires 6+ years of verification experience.

Responsibilities

Primary responsibilities include ownership of verification plans, environments, and CI/CD regression for connectivity IPs and chiplets.

• Develop and execute verification plans for PHYs, controllers, and chiplets.
• Create and maintain SystemVerilog/UVM testbenches and compliant test cases for block and chip levels.
• Maintain regression and CI/CD pipelines; manage coverage analysis and regression runs.
• Collaborate with design and architecture teams on microarchitecture, test plans, and coverage reviews.
• Integrate and coordinate 3rd-party VIPs; track feature and bug requests.
• Lead and mentor junior verification engineers.
• Develop and maintain DPI-based firmware simulation and GLS environments for functional and power simulations.
• Ensure IP compliance with Ethernet (IEEE 802.3) and relevant standards; monitor standards body progress.

Requirements

Must-have technical skills and experience:

• Strong expertise in SystemVerilog and UVM for test environment and assertion coding.
• Hands-on experience verifying serial transmission protocols and products (retimers, gearboxes, Ethernet PMA/PCS preferred).
• Proficiency with regression management and coverage analysis tools.
• 3+ years working on Ethernet 802.3 clauses related to 100G/200G/400G/800G, Auto-Negotiation and Link Training.
• Experience verifying 3rd-party mixed-signal IPs and integrating VIPs.
• Proven ability to automate verification tasks and improve verification quality and efficiency.

Nice-to-have:

• Knowledge of DRAM controllers/PHYs and HBM memory.
• Experience in startup environments and delivering products under tight schedules.

Education Requirements

Master's or Ph.D. in Electrical Engineering or a related field. The posting specifies 6+ years of experience.

About the Company

Company: Beacon Industries

Technology/engineering company focused on analog and mixed-signal integrated circuit design and custom IC layout (SerDes, SRAM, high-speed interfaces), using Synopsys/Cadence EDA tools for design, simulation, verification, and silicon validation.