Staff Digital Verification Engineer

Job Title

Staff Digital Verification Engineer

Role Summary

Lead verification of complex digital blocks and major SoC features for power-management products. Work cross-functionally with architecture, RTL design, firmware, analog, validation, and systems teams to deliver coverage-driven verification from planning through closure.

Experience Level

Senior - 7+ years of relevant digital design verification experience or equivalent directly applicable experience.

Responsibilities

Primary responsibilities include ownership of verification activities, developing reusable environments, and driving coverage closure.

• Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
• Create feature-based verification plans from product and microarchitecture specifications; identify gaps and risks.
• Build and extend reusable SystemVerilog/UVM environments: sequences, monitors, scoreboards, checkers, assertions, and coverage models.
• Develop constrained-random and directed tests for normal operation, error handling, recovery, and system-level interactions.
• Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.
• Debug RTL, testbench, assertion, integration, and regression failures and collaborate with design and firmware teams to verify fixes.
• Automate regression, triage, reporting, and analysis workflows using scripting and engineering tools.
• Communicate status, risks, dependencies, and closure evidence; provide technical guidance to less-experienced engineers.

Requirements

Must-have technical skills and experience; preferred skills listed separately.

• 7+ years of relevant digital design verification experience or equivalent directly applicable experience.
• Strong proficiency in SystemVerilog, UVM, constrained-random verification, functional coverage, and SystemVerilog Assertions (SVA).
• Proven experience developing and debugging reusable UVM environments, sequences, scoreboards, checkers, and coverage models.
• Strong RTL and testbench debug skills and ability to isolate design vs environment vs firmware vs spec issues.
• Solid knowledge of digital design fundamentals: state machines, clocks/resets, interrupts, register interfaces, memories, and CDC.
• Proficiency with Linux and at least one scripting language (Python, Bash, Perl, or Tcl).
• Ability to work independently and collaborate across architecture, design, firmware, analog, validation, and systems teams.

Nice-to-have:

• Experience verifying complex SoCs, power-management ICs, voltage regulators, or mixed-signal products.
• Experience with RTL interfaces to embedded processors, memory-mapped peripherals, and firmware-controlled features.
• Familiarity with PMBus, AVSBus, SVID/SVI3, I2C, SPI, or similar protocols.
• Experience with Cadence Xcelium, SimVision, vManager, JasperGold, Synopsys VCS, Verdi, or similar tools.
• Experience with formal verification, gate-level simulation, silicon bring-up, or pre-/post-silicon correlation.
• Experience improving regression infrastructure, coverage analytics, failure triage, or verification automation.

Education Requirements

Bachelor's or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or equivalent directly applicable practical experience.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.