Staff Digital Verification Engineer

Role Summary

The Staff Digital Verification Engineer will take ownership of IP and SoC-level verification. The role requires working on complex challenges collaboratively with cross-functional teams, focusing on PVT sensing IP for next-generation semiconductor products.

Experience Level

Mid-level, with 5–8 years of hands-on digital verification experience.

Responsibilities

The main responsibilities include:

• Planning and executing IP/SoC verification using UVM environments.
• Developing behavioral models aligned with specifications.
• Writing constrained-random and directed test cases and assertions.
• Driving code and functional coverage to target metrics.
• Running Gate-Level Simulations (GLS) and performing checks.
• Collaborating with design and firmware teams.

Requirements

Applicants should meet the following requirements:

• Strong proficiency in Verilog, SystemVerilog, and UVM.
• Hands-on experience with IP/SoC verification.
• Expertise in writing and debugging SystemVerilog Assertions (SVA).
• Familiarity with Shell scripting, Makefiles, and Python.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.