Staff Digital Design Engineer – SoC Low Power, Clocking & Integration

Job Title

Staff Digital Design Engineer – SoC Low Power, Clocking & Integration

Role Summary

Senior digital-IC design engineer responsible for architecting, designing, and integrating low-power and clocking infrastructure in complex Wireless MCU SoCs. The role works on SoC-level power and clock domains, RTL for infrastructure controllers, interconnects, and subsystem integration across digital, analog, and backend teams.

Experience Level

Senior; typically 10–20 years of professional experience in digital CMOS IC design.

Responsibilities

Key responsibilities include architecture, RTL delivery, integration, and validation of low-power and clocking infrastructure for SoCs.

• Define and implement SoC low-power architecture: power domains, retention, isolation, level shifters, and power sequencing.
• Develop and integrate UPF/CPF-based power intent across subsystem and SoC hierarchies.
• Design and integrate clocking infrastructure: clock generation, distribution, gating, muxing, resets, and monitoring.
• Drive RTL design and integration of power management, clock, and reset controllers and related infrastructure IP.
• Architect and integrate on-chip interconnects and bus fabrics (AXI, AHB, APB) and connect processors, memories, peripherals, accelerators, and third-party IPs.
• Lead small design teams and conduct architecture, design, and verification reviews throughout the project lifecycle.
• Analyze and debug low-power, clocking, CDC/RDC, timing, and protocol issues in simulation, emulation, synthesis, and silicon bring-up.
• Coordinate subsystem and SoC integration activities and support silicon validation and bring-up efforts.
• Collaborate with backend and analog/mixed-signal teams to meet power, performance, and area targets.

Requirements

Must-have technical skills and experiences for successful performance in this role.

• Proven ability to lead small teams designing complex digital subsystems.
• Strong RTL design expertise in Verilog / SystemVerilog.
• Deep understanding of SoC clocking architectures, clock domain crossing (CDC), reset domain crossing (RDC), synchronization techniques, and timing considerations.
• Extensive experience with low-power design methodologies, including power gating, retention, isolation, level shifting, and power-aware verification (UPF/CPF implementation moved to Responsibilities).
• Experience with industry-standard on-chip bus protocols (AXI, AHB, APB) and interconnect architectures.
• Experience integrating complex subsystems, processor clusters, memory subsystems, and third-party IP into large SoCs.
• Experience with logic simulation (RTL and gate-level), waveform/debug tools, logic synthesis, and timing constraints.
• Practical experience with scripting and automation (Python, Perl, Tcl) and with revision control systems (Perforce, Git, Methodics).
• Strong verbal and written communication skills and demonstrated high individual output.

Nice-to-have:

• Experience with AI-powered tools to enhance productivity, analysis, or decision-making.

Education Requirements

BS or MS in Electrical Engineering (the posting specifies BS/MS in Electrical Engineering).

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.