Staff Digital Design Engineer

Job Title

Staff Digital Design Engineer

Role Summary

Lead the architecture, implementation, and integration of digital subsystems for Automotive Ethernet PHY products (including 10BASE-T1S, 100BASE-T1, 1000BASE-T1 and multi-gig SerDes). The role owns digital micro-architecture, RTL implementation, and end-to-end system integration with mixed-signal and firmware teams.

Experience Level

Senior — requires 7+ years of relevant digital design experience.

Responsibilities

Primary responsibilities span architecture, RTL development, verification planning, and system bring-up for Automotive Ethernet PHYs.

• Define and own digital subsystem micro-architecture: PCS pipelines, encoding/decoding, scramblers/descramblers, CRC engines, framing, and packet processing.
• Partition system-level functionality between digital, analog/mixed-signal, and firmware; lead feasibility and trade-off studies (power, performance).
• Develop high-quality RTL (Verilog/SystemVerilog) for control, datapath, and protocol logic and provide synthesis guidance.
• Drive digital front-end flows: linting, CDC/RDC analysis, reset architecture, timing constraints, and logic optimization.
• Collaborate with design verification to define coverage goals, corner cases, and verification plans.
• Work with mixed-signal teams on control interfaces, calibration engines, register programming, and digital-analog interaction models.
• Contribute to board/system bring-up, compliance testing, post-silicon validation, and debugging.
• Define and implement automotive-quality and functional-safety features: BIST, diagnostics, timeout recovery, watchdogs, and fault reporting; participate in FMEDA/DFA.

Requirements

Technical must-haves and desirable skills for successful performance in the role.

Must-have:

• Expert Verilog/SystemVerilog RTL design for protocol and control logic.
• Strong experience with high-speed digital logic, finite state machines, and protocol datapaths.
• Practical knowledge of IEEE 802.3 Ethernet PCS, link training, and related system control flows.
• Experience with synthesis, static timing analysis (STA), and CDC/RDC methodologies.
• Familiarity with SoC/PHY interface logic (MII/RMII/RGMII/GMII/XGMII) and processor-based SoC design.
• Proven track record across multiple production tape-outs and silicon bring-ups.

Nice-to-have / Preferred:

• Experience with Automotive Ethernet variants (10BASE-T1S, 100BASE-T1, 1000BASE-T1, 10GBASE-T1).
• Familiarity with firmware-driven PHY initialization and configuration flows.
• Strong post-silicon debugging skills (logic analyzers, protocol analyzers) and validation experience.
• Background in safety-critical digital logic design and automotive functional-safety processes.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related discipline is required (as stated). No alternative equivalent-degree language was provided in the source.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.