Staff DFT Engineer

Job Title

Staff DFT Engineer

Role Summary

Member of the Cores DFT team owning ATPG/DFT responsibilities for the next generation of AMD high-performance cores. The role works across architecture, IP design, physical design, and product engineering to enable first-pass silicon success.

This is a technical, hands-on engineering role focused on test generation, debug, silicon bring-up, and improving test quality and efficiency.

Experience Level

Senior-level engineer. (Title indicates senior/Staff level; specific years of experience not stated.)

Responsibilities

Primary responsibilities include development, validation, and debug of DFT solutions for large, high-performance cores.

• Own ATPG/DFT delivery for core designs, including stuck-at, at-speed, and path-delay tests.
• Develop and validate scan compression strategies and flows.
• Debug low-coverage and DRC violations; propose and implement efficient fixes.
• Perform logic design and verification tasks using Verilog.
• Investigate and resolve complex test-pattern failures and simulation issues.
• Support silicon bring-up and participate in post-silicon debug and validation.
• Collaborate with architecture, IP, physical design, and product teams to meet timing and test objectives.
• Use Linux and scripting (Perl, TCL, etc.) to develop and automate DFT flows.
• Communicate technical findings and trade-offs clearly to cross-functional teams.

Requirements

Must-have technical skills, practical experience, and work authorization.

• Proven experience with industrial DFT tools and ATPG flows (stuck-at, at-speed, path-delay) and scan compression.
• Proficient in RTL/logic design and debugging using Verilog.
• Experience debugging test-pattern issues and simulation failures; familiar with low coverage analysis and DRC fixes.
• Experience with silicon bring-up and post-silicon debug activities.
• Comfortable in Linux and proficient with scripting (Perl, TCL, Python, or similar) to build and automate flows.
• Knowledge of DFT practices and trade-offs, including JTAG, MBIST, and test-quality vs. test-time considerations.
• Strong presentation, communication skills, and ownership mentality.
• Must be eligible to work in the United States without employer visa sponsorship.

Nice-to-have:

• Hands-on experience with commercial test-generation tools for large complex designs (e.g., Tessent scan/ATPG flows).
• Strong fundamentals in test pattern translation, yield learning, logic diagnosis, scan compression, LBIST/MBIST.
• Experience validating DFT features on ATE and direct silicon bring-up on advanced nodes (7nm or smaller).
• Experience applying agentic AI tools to accelerate flow development, debugging, and delivery timelines.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering (the posting lists Bachelors or Master's in computer engineering/Electrical Engineering). No mention of acceptable equivalent-experience language beyond these degrees.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.