Staff DFT Engineer

Job Title

Staff DFT Engineer

Role Summary

Lead the definition and delivery of Design-for-Test (DFT) strategy for complex SoCs from architecture through production silicon. Responsible for test quality, coverage, and silicon readiness while coordinating with design, physical design, verification, ATE, and manufacturing teams.

Experience Level

Senior — typically 7+ years of hands-on DFT experience driving architecture and silicon bring-up.

Responsibilities

Deliver end-to-end DFT solutions and provide technical leadership across chips and teams.

• Define DFT architecture at chip and subsystem level; specify scan, compression, LBIST, MBIST, boundary scan, and test access strategies.
• Drive testability requirements early in the RTL phase and balance coverage, test time, power, area, and schedule tradeoffs.
• Lead scan insertion, stitching, DRC closure, ATPG (stuck-at, transition, path delay), test compression, and pattern optimization.
• Own DFT signoff including coverage, IR drop, power, and timing impacts; debug issues across RTL, synthesis, P&R, and gate-level flows.
• Generate, analyze, and optimize ATPG patterns; review fault coverage, pattern volume, and test time; diagnose coverage holes.
• Support first-silicon bring-up, failure analysis, yield ramp, and drive ECOs for DFT-related silicon issues.
• Act as technical lead and mentor for DFT engineers; define best practices, checklists, and reusable methodologies.
• Collaborate with RTL designers, PD, verification, product engineering, ATE, and manufacturing to communicate DFT requirements and risks.

Requirements

Must-have technical skills and experience to perform the role; preferred items listed separately.

• Proven track record leading DFT efforts through architecture to silicon bring-up for complex SoCs.
• Deep hands-on expertise in ATPG, scan chain compression and stitching, DFT rule checks, and low-power DFT techniques.
• Experience with Memory BIST (MBIST) including repair mechanisms, boundary-scan (IEEE 1149.1), JTAG/TAP integration, and analog DFT strategies.
• Experience applying DFT-specific STA constraints and understanding impacts on timing, power, and routing.
• Proficient with industry DFT EDA tools (e.g., Cadence, Siemens) and strong scripting/automation skills in Python, Tcl, and/or Perl.
• Solid understanding of digital design fundamentals (RTL design, lint/CDC, low-power checks) and the full ASIC design flow.
• Strong problem-solving, debugging, and communication skills; ability to work in cross-functional teams.
• Willingness to travel for product support and collaboration (approximately 10%).

Education Requirements

Bachelor's or Master’s degree in Electrical/Electronics Engineering or a closely related field.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.