Staff DFT Engineer

Job Title

Staff DFT Engineer

Role Summary

Lead DFT strategy and execution for complex SoCs from architecture through silicon bring-up and production. Work as the technical DFT lead across design, physical design, verification, product engineering, ATE, and manufacturing teams to ensure test quality, coverage, and silicon readiness.

Experience Level

Senior — typically 7+ years of hands-on DFT experience leading end-to-end SoC DFT execution.

Responsibilities

Deliver and own DFT architecture, implementation, signoff, and production support; provide technical leadership and cross-functional coordination.

• Define chip- and subsystem-level DFT architecture (scan, compression, LBIST, MBIST, boundary scan, test access).
• Drive testability requirements early in RTL design and balance coverage, test time, power, area, and schedule trade-offs.
• Lead scan insertion, stitching, DRC closure, ATPG (stuck-at, transition, path delay), compression, and pattern optimization.
• Own DFT signoff including coverage analysis, IR drop, power, and timing impacts; diagnose and resolve DFT issues across RTL, synthesis, P&R, and gate-level stages.
• Generate, analyze, and optimize ATPG patterns; review fault coverage, pattern volume, and test time; drive fixes for coverage holes.
• Support first-silicon bring-up, failure analysis, yield ramp, and ATE-related debug; drive ECOs for DFT-related silicon issues.
• Provide technical leadership: mentor engineers, define best practices, and conduct design reviews.
• Collaborate with RTL designers, PD, verification, product engineering, ATE, and manufacturing to communicate DFT requirements and risks.

Requirements

Must-have technical skills and experience. Nice-to-have items listed separately.

• Proven track record leading DFT teams through architecture, implementation, and silicon bring-up for complex SoCs.
• Deep hands-on expertise in ATPG, scan chain insertion and compression, DFT rule checks (DFT DRC), and signoff processes.
• Experience with LBIST, MBIST (including repair), boundary-scan (IEEE 1149.1), JTAG/TAP integration, and DFT-specific STA constraints.
• Proficient with industry DFT EDA tools (examples: Cadence, Siemens toolsets) and automation scripting (Perl, Tcl, Python).
• Solid understanding of digital design fundamentals (RTL, lint/CDC, low-power checks) and the full ASIC flow.
• Strong problem-solving skills for debugging complex DFT issues across design flows and manufacturing; effective cross-functional communication.
• Willingness to travel approximately 10% for cross-site collaboration and bring-up activities.

• Nice-to-have: high-volume production test and ATE bring-up experience, exposure to safety-critical standards (e.g., ISO 26262) from a test standpoint, on-chip debug/trace experience, prior experience leading small DFT teams.

Education Requirements

Bachelor's or Master’s degree in Electrical/Electronics Engineering or a closely related field.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.