Staff Design Verification Engineer — SerDes / AMS / Mixed‑Signal IPs

Job Title

Staff Design Verification Engineer — SerDes / AMS / Mixed‑Signal IPs

Role Summary

Execute and own verification for SerDes, AMS and mixed‑signal IPs within the Central Engineering AMS IP team to ensure functional correctness, coverage closure, and reliable integration into SoCs across advanced process nodes (5nm/3nm/2nm).

Work closely with Design, AMS, Firmware and Architecture teams to develop UVM testbenches, debug multi‑layer failures, stabilize regressions, and adopt verification best practices and new flows.

Experience Level

Senior / Staff level. Typical experience: 5–9 years in verification or AMS/mixed‑signal design environments (degree-related guidance is in Education Requirements).

Responsibilities

Primary responsibilities include ownership of verification activities, testbench development, and cross‑team collaboration to drive functional and coverage closure.

• Execute and own verification of SerDes, AMS and mixed‑signal IPs across advanced nodes (5nm/3nm/2nm).
• Design and maintain UVM-based testbenches, sequences, checkers, and coverage models.
• Verify high‑speed interfaces (PCIe, Ethernet, DDR, D2D, PHY components including PAM4/PAM2).
• Support verification of calibration, link training, power modes and firmware‑driven flows.
• Debug failures across RTL, AMS models, VIPs, and testbench infrastructure; analyze regressions and improve stability.
• Collaborate with Design, AMS, Firmware and Architecture teams to resolve issues and clarify intent.
• Assist with GLS bring‑up, power‑aware verification, and timing‑related checks as required.
• Follow and contribute to verification methodologies and best practices; adopt new tools and flows.

Requirements

Must-have technical skills and experience.

• Strong hands‑on experience with SystemVerilog and UVM.
• Knowledge of SerDes or PHY architectures and AMS / mixed‑signal concepts.
• Experience with verification IPs (VIPs) and regression/coverage analysis.
• Ability to debug across multiple abstraction layers (RTL, AMS, VIPs, firmware).
• Experience integrating register models and firmware interaction.
• Good communication skills, strong ownership, and ability to work independently and cross‑functionally.

Nice-to-have:

• Exposure to AMS verification tools and modeling techniques.
• Experience with link training, calibration logic, or DSP‑analog interaction.
• Exposure to GLS, low‑power verification, post‑silicon debug, automation, or scripting.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related field with ~5–7 years of relevant experience; or Master’s degree or PhD in Computer Science, Electrical Engineering or related field with ~6–9 years of relevant experience in verification and/or AMS/mixed‑signal design environments.

Note: This position may require eligibility to access export‑controlled technology; candidates may be subject to export license review. Candidates should also be aware that use of AI tools during interviews is prohibited.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.