Staff Design Verification Engineer

Job Title

Staff Design Verification Engineer

Role Summary

Lead and deliver functional verification for complex FPGA/ASIC IPs, subsystems, and SoC-level designs. Work within the verification team and across RTL, architecture, firmware, and validation teams to plan verification strategy, implement reusable verification environments, drive closure, and support silicon bring-up.

Experience Level

Senior-level. The role expects extensive experience (posting indicates 8+ years) in ASIC/FPGA functional verification.

Responsibilities

Primary responsibilities focus on verification planning, environment development, closure, and technical leadership.

• Define verification methodologies, test strategies, coverage goals, and closure criteria for IP, subsystem, and SoC deliverables.
• Architect and develop SystemVerilog/UVM verification environments, reusable components, scoreboards, assertions, and coverage models.
• Lead verification planning, execution, regression management, and sign-off for complex designs.
• Drive closure through functional and code coverage, regression analysis, and risk assessment.
• Debug complex RTL, integration, low-power, timing, and gate-level simulation issues.
• Collaborate with architects, RTL designers, firmware, validation, and program management to resolve design and integration issues.
• Provide technical leadership for verification methodology, automation, and infrastructure improvements.
• Mentor and guide verification engineers; perform design and verification reviews to raise team capability.
• Support silicon bring-up, failure analysis, and root-cause investigations as required.

Requirements

Must-have technical skills and experience required to perform the role.

• 8+ years of ASIC/FPGA functional verification experience (as stated in posting).
• Strong expertise in SystemVerilog, UVM, and assertion-based verification.
• Proven experience leading verification of complex IPs, subsystems, or SoCs from planning through sign-off.
• Strong debugging skills in RTL, gate-level, and system-level verification environments.
• Experience with constrained-random verification, coverage-driven verification, and regression management.
• Proficiency in scripting (Python, Perl, Shell, or similar) for automation and infrastructure tasks.
• Excellent communication and cross-functional collaboration skills; ability to mentor and lead technical initiatives.
• Preferred: experience with PCIe, USB, MIPI CSI/DSI, Ethernet, SerDes or other high-speed protocols; low-power verification (UPF/CPF); GLS, timing validation, and post-silicon debug.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field (as stated). The posting specifies degree-level education in relevant engineering disciplines.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.