Staff Design Verification Engineer – Coherent Interconnect

Job Title

Staff Design Verification Engineer – Coherent Interconnect

Role Summary

Own verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. The role is aligned to the Interconnect horizontal area and covers protocol correctness, coherent data movement, QoS, ordering, and subsystem integration across multiple interface types.

This is a Staff individual-contributor role expected to define verification strategy, identify gaps early, solve complex verification problems, and raise the quality bar for the broader interconnect verification effort.

Experience Level

Senior-level. Minimum guidance: 7+ years of ASIC or SoC design verification experience (per job minimums).

Responsibilities

Primary responsibilities include verification planning, environment development, cross-team collaboration, and driving coverage and debug to signoff.

• Own verification planning and execution from block-level verification through subsystem integration for a scalable cache-coherent interconnect.
• Develop and maintain verification environments, checkers, scoreboards, stimulus, and coverage for coherent traffic, ordering, backpressure, flow control, and error handling.
• Verify protocol adaptation and integration across multiple interface types and bridge paths (conversion, buffering, deinterleaving, data movement).
• Drive verification of QoS handling, arbitration policy, virtual-network behavior, and transport-level correctness.
• Define directed and constrained-random test scenarios exposing corner cases in coherency, concurrency, ordering, credits, and integration.
• Partner with architecture, design, formal, and software teams to clarify requirements and accelerate debug and signoff.
• Analyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Improve verification methodology, infrastructure, and productivity across the interconnect verification effort.
• Contribute to reviews of specs, verification plans, coverage closure, and debug strategy.

Requirements

Must-have technical skills and experience required for immediate contribution.

Must-have:

• 7+ years experience in ASIC or SoC design verification.
• Hands-on experience with SystemVerilog and UVM-based verification.
• Strong understanding of cache-coherent systems, on-chip interconnects, or memory-system verification.
• Experience verifying protocol behavior: ordering, flow control, backpressure, buffering, arbitration, and error handling.
• Experience building reusable testbench components, assertions, coverage models, and debug infrastructure.
• Strong debugging skills and ability to root-cause issues across specification, RTL, and testbench layers.
• Ability to work effectively with architecture, design, and verification teams in a fast-paced environment.

Nice-to-have:

• Experience with coherent interconnects, NoCs, memory fabrics, or large subsystem integration.
• Familiarity with protocols such as AXI, CHI, CXL, UCIe, or similar high-performance interfaces.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.
• Experience with protocol-conversion or bridge-heavy subsystems.
• Familiarity with Python or other scripting languages for DV infrastructure and automation.
• Experience mentoring other engineers and improving team-wide verification quality.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (BS/MS in EE, CE, or CS explicitly mentioned).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.