Staff Design Verification Engineer – Coherent Interconnect

Job Title

Staff Design Verification Engineer – Coherent Interconnect

Role Summary

Drive verification of a scalable, cache-coherent interconnect subsystem used in high-performance SoCs. Own verification planning and execution from block-level through subsystem integration and work across architecture, design, formal, and software teams to close ambiguities and accelerate signoff.

Experience Level

Senior-level individual contributor. The role expects 7+ years of ASIC/SoC design verification experience.

Responsibilities

Primary responsibilities include planning, implementing, and executing verification strategies for coherent interconnects and adjacent protocol-conversion subsystems.

• Own verification plans and execution for a cache-coherent interconnect subsystem, from block verification to subsystem integration.
• Develop and maintain verification environments, checkers, scoreboards, stimulus, and coverage models for coherency, ordering, flow control, and error handling.
• Verify protocol adaptation, buffering, deinterleaving, and integration across multiple interface types and bridge paths.
• Drive verification of QoS, arbitration, virtual-network behavior, and transport-level correctness.
• Define directed and constrained-random tests to expose corner cases in coherency, concurrency, ordering, and credits.
• Analyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Improve verification methodology, infrastructure, and productivity across the interconnect verification effort.
• Contribute to review quality for specs, verification plans, coverage closure, and debug strategy.

Requirements

Must-have technical skills and experience for immediate contribution.

• 7+ years of ASIC or SoC design verification experience (listed under Experience Level).
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Deep understanding of cache-coherent systems, on-chip interconnects, or memory-system verification.
• Experience verifying ordering, flow control, backpressure, buffering, arbitration, and error handling.
• Experience building reusable testbench components, assertions, coverage models, and debug infrastructure.
• Strong debugging and root-cause analysis skills spanning specification, RTL, and testbench layers.
• Ability to work effectively across architecture, design, formal, and verification teams in a fast-moving environment.

Nice-to-have:

• Experience with coherent interconnects, NoCs, memory fabrics, or large subsystem integration.
• Familiarity with industry protocols such as AXI, CHI, CXL, UCIe, or similar high-performance interfaces.
• Experience with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.
• Experience verifying protocol-conversion or bridge-heavy subsystems.
• Familiarity with Python or other scripting languages for DV infrastructure and automation.
• Experience mentoring other engineers and raising team-wide verification quality.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (BS/MS in EE/CE/CS are listed). No explicit equivalent-experience language provided.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.