Staff Design Verification Engineer

Job Title

Staff Design Verification Engineer

Role Summary

Member of the design verification team responsible for pre-silicon verification of complex SoC or subsystem products. The role defines verification architecture, drives DV flows and methodologies, and leads verification from planning through closure.

Works cross-functionally with emulation, FPGA, firmware and design teams to ensure end-to-end system correctness and performance.

Experience Level

Senior-level — typically requires 8+ years of experience in digital pre-silicon verification.

Responsibilities

Key responsibilities include:

• Lead pre-silicon verification for complex SoC or subsystem designs, from strategy and planning to execution and closure.
• Architect and implement UVM-based testbenches, scalable DV flows, and verification infrastructures.
• Define and execute test plans; drive functional and code coverage closure across block and subsystem levels.
• Verify microprocessor-based systems, AI/ML accelerators, and high-speed peripherals; perform system-level use-case and performance validation.
• Collaborate with emulation, FPGA, firmware, and design teams for end-to-end validation and debug.
• Apply formal techniques and set up formal flows for IP and subsystem checks.
• Lead NoC/interconnect verification, including coverage analysis and optimization.
• Support gate-level simulations with timing annotation and power-aware verification activities.
• Develop and validate end-to-end scenarios and system-level verification strategies using modern techniques (emulation, portable stimulus, virtual platforms).
• Drive verification methodology improvements and mentor other engineers.

Requirements

Must-have skills and experience; nice-to-have items noted.

• Strong hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven track record of verification closure using functional and code coverage metrics at block and subsystem levels.
• Experience in NoC, bus, and interconnect verification, including coverage analysis and optimization.
• Hands-on experience in power-aware verification using UPF, including power analysis and optimization.
• Exposure to formal verification and experience setting up formal flows and connectivity checks.
• Familiarity with gate-level simulations (GLS) with timing annotation.
• Experience architecting testbench environments and implementing scalable DV flows and methodologies.
• Proficiency in C/C++, SystemC and scripting (Python, TCL, Shell) for verification automation.
• Excellent communication, collaboration, and problem-solving skills; ability to work across global teams.
• Nice-to-have: familiarity with ARM, RISC-V, Tensilica processors, AI/ML or GPU architectures, emulation, portable stimulus, and virtual platforms.

Education Requirements

B.Tech or M.Tech in Electrical/Computer Engineering, Computer Science, or a related technical field. The posting expects approximately 8+ years of relevant pre-silicon verification experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.