Staff Design Verification Engineer

Job Title

Staff Design Verification Engineer

Role Summary

Join the silicon design verification team to lead end-to-end functional verification for mixed-signal ASICs, from block-level to chip-level. The role works closely with digital and analog designers, systems, firmware/software, and manufacturing test to deliver validated silicon and verification infrastructure.

This position emphasizes rigorous verification methodology, automation, and cross-functional collaboration in a technical, fast-paced environment.

Experience Level

Senior-level. Typical guidance: Bachelor's +7 years, Master's +5 years, PhD +3 years of relevant experience, or equivalent industry experience.

Responsibilities

Deliver, execute, and improve verification strategies and infrastructure for complex mixed-signal designs.

• Develop comprehensive verification plans aligned with design and system requirements.
• Perform functional verification of custom mixed-signal ASICs at block and chip level.
• Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
• Create directed and constrained-random test suites and drive coverage closure.
• Execute regressions; conduct failure analysis, regression triage, and debug functional and timing issues.
• Run and debug gate-level simulations, including timing back-annotation and timing violations.
• Develop and maintain digital and mixed-signal behavioral models to support verification.
• Support verification flow, automation, and infrastructure development.
• Collaborate cross-functionally with digital/analog design, systems, firmware/software, and manufacturing test teams.
• Contribute to both pre-silicon verification and post-silicon validation and improve verification methodologies.

Requirements

Core technical skills and practical experience required; preferred items are listed separately.

Must-have:

• Significant industry experience in silicon design and/or ASIC verification.
• Strong proficiency with HDLs: Verilog and/or VHDL.
• Strong proficiency with HVLs: SystemVerilog with UVM (or OVM/AVM/Vera).
• Solid understanding of digital design principles and system architecture.
• Experience with testbench architecture, stimulus generation, regression execution and debug.
• Experience with coverage analysis and driving coverage closure.
• Ability to analyze failures, debug complex issues, and work effectively in cross-disciplinary teams.

Nice-to-have:

• Experience verifying mixed-signal ASICs in complex SoC environments.
• Knowledge of signal processing concepts relevant to mixed-signal designs.
• Experience with SystemVerilog Assertions (SVA).
• Exposure to or hands-on experience with formal verification, hardware emulation/acceleration, and software-driven verification.

Education Requirements

Degree preferred: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Experience guidance provided in the posting: Bachelor's with 7+ years, Master's with 5+ years, PhD with 3+ years; equivalent practical industry experience is accepted.

About the Company

Company: Cirrus Logic

Headquarters: Austin, TX, United States

Designer and manufacturer of high-precision analog and mixed-signal integrated circuits, specializing in audio and voice processing solutions for consumer electronics and mobile devices, including audio codecs, converters, and SoCs.