Staff Design for Test (DFT) Engineer

Job Title

Staff Design for Test (DFT) Engineer

Role Summary

Senior DFT engineer responsible for DFT architecture, specification, implementation and verification for ASIC/SoC products. Work with product teams to deliver high coverage, low-power, and low-test-time solutions across product lines.

Based in Limerick, Ireland; role includes occasional travel for silicon bring-up and cross-site collaboration (approximately 10%).

Experience Level

Senior — expects extensive experience. Minimum stated experience: 10+ years in ASIC/SoC DFT.

Responsibilities

Deliver and validate DFT solutions across product lines, support pre- and post-silicon activities, and provide methodology and automation improvements.

• Define DFT specifications and architecture; implement using current methodologies and tools.
• Perform scan insertion, compression insertion, on-chip clock control insertion, and ATPG flow implementation.
• Generate and verify Automatic Test Pattern Generation (ATPG) patterns with high coverage and low test time.
• Support pre-silicon and post-silicon verification, silicon bring-up, failure analysis and debug.
• Provide methodology support, DFT flow automation and process/innovation improvements.
• Conduct gate-level simulation with SDF for test verification.
• Mentor junior engineers and collaborate with cross-functional teams.

Requirements

Must-have technical skills and experience required for immediate contribution; preferred skills improve productivity or fit.

• Must-have: 10+ years of directly related ASIC/SoC DFT experience.
• Must-have: Expert knowledge of DFT architecture and planning; strong experience with scan, test compression, at-speed test, MBIST and LBIST.
• Must-have: Hands-on experience with Tessent DFT tools and experience in scan/ATPG/DFT verification flows.
• Must-have: Experience with scan insertion, compression insertion, on-chip clock control insertion, ATPG, and gate-level simulation with SDF.
• Must-have: Silicon test bring-up support and failure analysis/debug skills.
• Must-have: Scripting proficiency (Perl, Python, Tcl) and strong verbal/written communication skills; team-player attitude.

• Nice-to-have: Experience with Cadence and Synopsys DFT tools.
• Nice-to-have: Familiarity with IEEE 1149/JTAG, static timing analysis, synthesis and DFT insertion.
• Nice-to-have: Experience with BIST, low-power scan techniques and UPF.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.